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Sreesan Venkatakrishnan
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San Jose, CA, US
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Patents Grants
last 30 patents
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Patent Grant
Deadlock detection and prevention for routing packet-switched nets...
Patent number
12,327,077
Issue date
Jun 10, 2025
Xilinx, Inc.
Sreesan Venkatakrishnan
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Optimizing hardware design throughput by latency aware balancing of...
Patent number
11,604,751
Issue date
Mar 14, 2023
Xilinx, Inc.
Brian Guttag
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Post-placement and post-routing physical synthesis for multi-die in...
Patent number
10,839,125
Issue date
Nov 17, 2020
Xilinx, Inc.
Sreesan Venkatakrishnan
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Physical synthesis for multi-die integrated circuit technology
Patent number
10,496,777
Issue date
Dec 3, 2019
Xilinx, Inc.
Sreesan Venkatakrishnan
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
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Patent Application
DEADLOCK DETECTION AND PREVENTION FOR ROUTING PACKET-SWITCHED NETS...
Publication number
20230359801
Publication date
Nov 9, 2023
Xilinx, Inc.
Sreesan Venkatakrishnan
G06 - COMPUTING CALCULATING COUNTING