Sri Chaitra Chavali

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Package embedded magnetic inductor structures and manufacturing tec...
- Patent number 12,132,015
- Issue date Oct 29, 2024
- Intel Corporation
- William J. Lambert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density organic interconnect structures
- Patent number 12,062,551
- Issue date Aug 13, 2024
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectively roughened copper architectures for low insertion loss c...
- Patent number 12,033,930
- Issue date Jul 9, 2024
- Intel Corporation
- Jieying Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,935,805
- Issue date Mar 19, 2024
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scalable high speed high bandwidth IO signaling package architectur...
- Patent number 11,869,842
- Issue date Jan 9, 2024
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Antenna package using ball attach array to connect antenna and base...
- Patent number 11,870,163
- Issue date Jan 9, 2024
- Intel Corporation
- Jimin Yao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures in package substrates
- Patent number 11,804,426
- Issue date Oct 31, 2023
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inductors for package substrates
- Patent number 11,764,150
- Issue date Sep 19, 2023
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid core substrate architecture for high speed signaling and FLI...
- Patent number 11,721,632
- Issue date Aug 8, 2023
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,664,290
- Issue date May 30, 2023
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device including fiber-containing build-up layers
- Patent number 11,664,313
- Issue date May 30, 2023
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density organic interconnect structures
- Patent number 11,631,595
- Issue date Apr 18, 2023
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wideband multi-pin edge connector for radio frequency front end module
- Patent number 11,611,164
- Issue date Mar 21, 2023
- Intel Corporation
- Zhenguo Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-thin, hyper-density semiconductor packages
- Patent number 11,430,724
- Issue date Aug 30, 2022
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of tall metal pillars using multiple photoresist layers
- Patent number 11,393,762
- Issue date Jul 19, 2022
- Intel Corporation
- Sri Chaitra J. Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer package-on-package (PoP) with solder array thermal contacts
- Patent number 11,387,175
- Issue date Jul 12, 2022
- Intel Corporation
- Debendra Mallik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Antenna package using ball attach array to connect antenna and base...
- Patent number 11,355,849
- Issue date Jun 7, 2022
- Intel Corporation
- Jimin Yao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density package substrate formed with dielectric bi-layer
- Patent number 11,276,634
- Issue date Mar 15, 2022
- Intel Corporation
- Srinivas V. Pietambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermally coupled package-on-package semiconductor packages
- Patent number 11,222,877
- Issue date Jan 11, 2022
- Intel Corporation
- Omkar Karhade
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density organic interconnect structures
- Patent number 11,195,727
- Issue date Dec 7, 2021
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low z-height, ultra-low dielectric constant air cavity based and mu...
- Patent number 11,196,165
- Issue date Dec 7, 2021
- Intel Corporation
- Sri Chaitra Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with underfill containment barrier
- Patent number 11,158,558
- Issue date Oct 26, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures in package substrates
- Patent number 11,107,757
- Issue date Aug 31, 2021
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic device including fiber-containing build-up layers
- Patent number 11,004,792
- Issue date May 11, 2021
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric electronic substrate and method of manufacture
- Patent number 10,980,129
- Issue date Apr 13, 2021
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Electrical interconnections with improved compliance due to stress...
- Patent number 10,903,137
- Issue date Jan 26, 2021
- Intel Corporation
- Siddharth K. Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density organic interconnect structures
- Patent number 10,685,850
- Issue date Jun 16, 2020
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structures in package substrates
- Patent number 10,672,693
- Issue date Jun 2, 2020
- Intel Corporation
- Sanka Ganesan
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Edge-firing antenna walls built into substrate
- Patent number 10,658,765
- Issue date May 19, 2020
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric electronic substrate and method of manufacture
- Patent number 10,624,213
- Issue date Apr 14, 2020
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE EMBEDDED MAGNETIC INDUCTOR STRUCTURES AND MANUFACTURING TEC...
- Publication number 20250022814
- Publication date Jan 16, 2025
- Intel Corporation
- William J. LAMBERT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES
- Publication number 20240355641
- Publication date Oct 24, 2024
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20240186202
- Publication date Jun 6, 2024
- Intel Corporation
- Rahul JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTUR...
- Publication number 20240088047
- Publication date Mar 14, 2024
- Intel Corporation
- Sanka GANESAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADAPTIVE TRACE WIDTH IN MULTI-LAYER SUBSTRATE PACKAGE
- Publication number 20240070366
- Publication date Feb 29, 2024
- Intel Corporation
- Nicholas HAEHN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANTENNA PACKAGE USING BALL ATTACH ARRAY TO CONNECT ANTENNA AND BASE...
- Publication number 20240063544
- Publication date Feb 22, 2024
- Intel Corporation
- Jimin Yao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20240030116
- Publication date Jan 25, 2024
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE WITH LOW-PERMITTIVITY CORE AND BUILDUP LAYERS
- Publication number 20230317592
- Publication date Oct 5, 2023
- Intel Corporation
- Brandon Christian Marin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20230245940
- Publication date Aug 3, 2023
- Intel Corporation
- Rahul JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES
- Publication number 20230223278
- Publication date Jul 13, 2023
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED MAGNETIC INDUCTOR AND METHOD
- Publication number 20230162902
- Publication date May 25, 2023
- Intel Corporation
- Numair Ahmed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20230138543
- Publication date May 4, 2023
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20220344247
- Publication date Oct 27, 2022
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CORELESS ELECTRONIC SUBSTRATES HAVING EMBEDDED INDUCTORS
- Publication number 20220293327
- Publication date Sep 15, 2022
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANTENNA PACKAGE USING BALL ATTACH ARRAY TO CONNECT ANTENNA AND BASE...
- Publication number 20220216611
- Publication date Jul 7, 2022
- Intel Corporation
- Jimin Yao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVELY ROUGHENED COPPER ARCHITECTURES FOR LOW INSERTION LOSS C...
- Publication number 20220102259
- Publication date Mar 31, 2022
- Intel Corporation
- Jieying Kong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES
- Publication number 20220059367
- Publication date Feb 24, 2022
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20210391232
- Publication date Dec 16, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES
- Publication number 20210351116
- Publication date Nov 11, 2021
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC DEVICE INCLUDING FIBER-CONTAINING BUILD-UP LAYERS
- Publication number 20210242132
- Publication date Aug 5, 2021
- Intel Corporation
- Sri Chaitra Jyotsna CHAVALI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING
- Publication number 20210193579
- Publication date Jun 24, 2021
- Intel Corporation
- Sanka Ganesan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID CORE SUBSTRATE ARCHITECTURE FOR HIGH SPEED SIGNALING AND FLI...
- Publication number 20210125932
- Publication date Apr 29, 2021
- Intel Corporation
- Sri Chaitra Jyotsna CHAVALI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE EMBEDDED MAGNETIC INDUCTOR STRUCTURES AND MANUFACTURING TEC...
- Publication number 20210125944
- Publication date Apr 29, 2021
- Intel Corporation
- William J. LAMBERT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH UNDERFILL CONTAINMENT BARRIER
- Publication number 20210111088
- Publication date Apr 15, 2021
- Intel Corporation
- Rahul Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTUR...
- Publication number 20210028116
- Publication date Jan 28, 2021
- Intel Corporation
- Sanka GANESAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INDUCTORS FOR PACKAGE SUBSTRATES
- Publication number 20210005550
- Publication date Jan 7, 2021
- Sri Chaitra Jyotsna CHAVALI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WIDEBAND MULTI-PIN EDGE CONNECTOR FOR RADIO FREQUENCY FRONT END MODULE
- Publication number 20200412041
- Publication date Dec 31, 2020
- Intel Corporation
- Zhenguo Jiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES
- Publication number 20200312675
- Publication date Oct 1, 2020
- Intel Corporation
- Sri Chaitra Jyotsna Chavali
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANTENNA PACKAGE USING BALL ATTACH ARRAY TO CONNECT ANTENNA AND BASE...
- Publication number 20200303822
- Publication date Sep 24, 2020
- Intel Corporation
- Jimin YAO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES
- Publication number 20200273784
- Publication date Aug 27, 2020
- Intel Corporation
- Debendra MALLIK
- H01 - BASIC ELECTRIC ELEMENTS

Sri Chaitra Chavali

Person

Patents Grantslast 30 patents

Package embedded magnetic inductor structures and manufacturing tec...

High density organic interconnect structures

Selectively roughened copper architectures for low insertion loss c...

Package with underfill containment barrier

Scalable high speed high bandwidth IO signaling package architectur...

Antenna package using ball attach array to connect antenna and base...

Integrated circuit structures in package substrates

Inductors for package substrates

Hybrid core substrate architecture for high speed signaling and FLI...

Package with underfill containment barrier

Microelectronic device including fiber-containing build-up layers

High density organic interconnect structures

Wideband multi-pin edge connector for radio frequency front end module

Ultra-thin, hyper-density semiconductor packages

Formation of tall metal pillars using multiple photoresist layers

Interposer package-on-package (PoP) with solder array thermal contacts

Antenna package using ball attach array to connect antenna and base...

High density package substrate formed with dielectric bi-layer

Thermally coupled package-on-package semiconductor packages

High density organic interconnect structures

Low z-height, ultra-low dielectric constant air cavity based and mu...

Package with underfill containment barrier

Integrated circuit structures in package substrates

Microelectronic device including fiber-containing build-up layers

Asymmetric electronic substrate and method of manufacture

Electrical interconnections with improved compliance due to stress...

High density organic interconnect structures

Integrated circuit structures in package substrates

Edge-firing antenna walls built into substrate

Asymmetric electronic substrate and method of manufacture

Patents Applicationslast 30 patents

PACKAGE EMBEDDED MAGNETIC INDUCTOR STRUCTURES AND MANUFACTURING TEC...

HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTUR...

ADAPTIVE TRACE WIDTH IN MULTI-LAYER SUBSTRATE PACKAGE

ANTENNA PACKAGE USING BALL ATTACH ARRAY TO CONNECT ANTENNA AND BASE...

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

SUBSTRATE WITH LOW-PERMITTIVITY CORE AND BUILDUP LAYERS

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES

STACKED MAGNETIC INDUCTOR AND METHOD

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES

CORELESS ELECTRONIC SUBSTRATES HAVING EMBEDDED INDUCTORS

ANTENNA PACKAGE USING BALL ATTACH ARRAY TO CONNECT ANTENNA AND BASE...

SELECTIVELY ROUGHENED COPPER ARCHITECTURES FOR LOW INSERTION LOSS C...

HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES

MICROELECTRONIC DEVICE INCLUDING FIBER-CONTAINING BUILD-UP LAYERS

EMBEDDED DIE ARCHITECTURE AND METHOD OF MAKING

HYBRID CORE SUBSTRATE ARCHITECTURE FOR HIGH SPEED SIGNALING AND FLI...

PACKAGE EMBEDDED MAGNETIC INDUCTOR STRUCTURES AND MANUFACTURING TEC...

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTUR...

INDUCTORS FOR PACKAGE SUBSTRATES

WIDEBAND MULTI-PIN EDGE CONNECTOR FOR RADIO FREQUENCY FRONT END MODULE

HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES

ANTENNA PACKAGE USING BALL ATTACH ARRAY TO CONNECT ANTENNA AND BASE...

ULTRA-THIN, HYPER-DENSITY SEMICONDUCTOR PACKAGES