Sridhar Krishnamurthy

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Timing closure of circuit designs for integrated circuits
- Patent number 10,366,201
- Issue date Jul 30, 2019
- Xilinx, Inc.
- Aaron Ng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating clock trees for a circuit design
- Patent number 10,068,048
- Issue date Sep 4, 2018
- Xilinx, Inc.
- Mehrdad Eslami Dehkordi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement and routing of clock signals for a circuit design
- Patent number 10,042,971
- Issue date Aug 7, 2018
- Xilinx, Inc.
- Mehrdad Eslami Dehkordi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock region partitioning and clock routing
- Patent number 9,330,220
- Issue date May 3, 2016
- Xilinx, Inc.
- Mehrdad E. Dehkordi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wide band deterministic interface
- Patent number 9,042,431
- Issue date May 26, 2015
- Altera Corporation
- Venkat Yadavalli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Implementing sub-circuits with predictable behavior within a circui...
- Patent number 8,448,122
- Issue date May 21, 2013
- Xilinx, Inc.
- Vishal Suthar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch based optimization during implementation of circuit designs f...
- Patent number 8,146,041
- Issue date Mar 27, 2012
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch based optimization during implementation of circuit designs f...
- Patent number 8,010,923
- Issue date Aug 30, 2011
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for generating network messages
- Patent number 8,005,886
- Issue date Aug 23, 2011
- JDS Uniphase Corporation
- Paul G. Jacobsen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Timing driven logic block configuration
- Patent number 7,926,016
- Issue date Apr 12, 2011
- Xilinx, Inc.
- Priya Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for directed physical implementation of a circ...
- Patent number 7,784,006
- Issue date Aug 24, 2010
- Xilinx, Inc.
- Arnaud Duthou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementation of alternate solutions in technology mapping and pla...
- Patent number 7,610,573
- Issue date Oct 27, 2009
- Xilinx, Inc.
- Vi Chi Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing driven logic block configuration
- Patent number 7,478,356
- Issue date Jan 13, 2009
- Xilinx, Inc.
- Priya Sundararajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of routing programmable logic devices to minimize programmi...
- Patent number 7,249,335
- Issue date Jul 24, 2007
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of routing programmable logic devices to minimize programmi...
- Patent number 7,143,384
- Issue date Nov 28, 2006
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits and methods for testing programmable logic devices using l...
- Patent number 7,111,214
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Kamal Chaudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of generating test designs for testing specific routing res...
- Patent number 7,058,919
- Issue date Jun 6, 2006
- Xilinx, Inc.
- Jay T. Young
- G01 - MEASURING TESTING
Information Patent Grant
Methods of resource optimization in programmable logic devices to r...
- Patent number 6,944,809
- Issue date Sep 13, 2005
- Xilinx, Inc.
- Andrew W. Lai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for specifying addressability and bus connecti...
- Patent number 6,910,002
- Issue date Jun 21, 2005
- Xilinx, Inc.
- Bart Reynolds
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable interface for a configurable system bus
- Patent number 6,754,760
- Issue date Jun 22, 2004
- Xilinx, Inc.
- Wilson Yee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bidirectional bus for use as an interconnect routing resource
- Patent number 6,661,812
- Issue date Dec 9, 2003
- Triscend Corporation
- Bart Reynolds
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for specifying address offsets and alignment i...
- Patent number 6,658,547
- Issue date Dec 2, 2003
- Triscend Corporation
- Bart Reynolds
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable processor system unit
- Patent number 6,467,009
- Issue date Oct 15, 2002
- Triscend Corporation
- Steven Paul Winegarden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FPGA CLE with two independent carry chains
- Patent number 6,107,827
- Issue date Aug 22, 2000
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable logic element with fast feedback paths
- Patent number 5,963,050
- Issue date Oct 5, 1999
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA repeatable interconnect structure with bidirectional and unidi...
- Patent number 5,942,913
- Issue date Aug 24, 1999
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed bus with tree structure for selecting bus driver
- Patent number 5,936,424
- Issue date Aug 10, 1999
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed bidirectional bus with multiplexers
- Patent number 5,847,580
- Issue date Dec 8, 1998
- Xilinx, Inc.
- Shekhar Bapat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmably bidirectional buffered interconnect circuit
- Patent number 5,844,424
- Issue date Dec 1, 1998
- Xilinx, Inc.
- Sridhar Krishnamurthy
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SYSTEMS AND METHODS FOR GENERATING NETWORK MESSAGES
- Publication number 20060267798
- Publication date Nov 30, 2006
- Finisar Corporation
- Paul G. Jacobsen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods of resource optimization in programmable logic devices to r...
- Publication number 20040030975
- Publication date Feb 12, 2004
- Xilinx, Inc.
- Andrew W. Lai
- G06 - COMPUTING CALCULATING COUNTING

Sridhar Krishnamurthy

Person

Patents Grantslast 30 patents

Timing closure of circuit designs for integrated circuits

Generating clock trees for a circuit design

Placement and routing of clock signals for a circuit design

Clock region partitioning and clock routing

Wide band deterministic interface

Implementing sub-circuits with predictable behavior within a circui...

Latch based optimization during implementation of circuit designs f...

Latch based optimization during implementation of circuit designs f...

Systems and methods for generating network messages

Timing driven logic block configuration

Method and apparatus for directed physical implementation of a circ...

Implementation of alternate solutions in technology mapping and pla...

Timing driven logic block configuration

Methods of routing programmable logic devices to minimize programmi...

Methods of routing programmable logic devices to minimize programmi...

Circuits and methods for testing programmable logic devices using l...

Methods of generating test designs for testing specific routing res...

Methods of resource optimization in programmable logic devices to r...

Method and apparatus for specifying addressability and bus connecti...

Programmable interface for a configurable system bus

Bidirectional bus for use as an interconnect routing resource

Method and apparatus for specifying address offsets and alignment i...

Configurable processor system unit

FPGA CLE with two independent carry chains

Configurable logic element with fast feedback paths

FPGA repeatable interconnect structure with bidirectional and unidi...

High speed bus with tree structure for selecting bus driver

High speed bidirectional bus with multiplexers

Programmably bidirectional buffered interconnect circuit

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR GENERATING NETWORK MESSAGES

Methods of resource optimization in programmable logic devices to r...