Sridhar Lakshmanamurthy

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method, apparatus and system for handling non-posted memory write t...
- Patent number 11,372,674
- Issue date Jun 28, 2022
- Intel Corporation
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for handling non-posted memory write t...
- Patent number 10,846,126
- Issue date Nov 24, 2020
- Intel Corporation
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sending packets with expanded headers
- Patent number 10,164,880
- Issue date Dec 25, 2018
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ultra low power architecture to support always on path to memory
- Patent number 9,916,876
- Issue date Mar 13, 2018
- Intel Corporation
- Suketu R. Partiwala
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and an apparatus with a sideband interface interconnecting...
- Patent number 9,753,875
- Issue date Sep 5, 2017
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing multiple decode options for a system-on-chip (SoC) fabric
- Patent number 9,658,978
- Issue date May 23, 2017
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting multiple channels of a single interface
- Patent number 9,489,329
- Issue date Nov 8, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing error handling support to legacy devices
- Patent number 9,448,870
- Issue date Sep 20, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggregating completion messages in a sideband interface
- Patent number 9,270,576
- Issue date Feb 23, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing a sideband message interface for system on a chip (SoC)
- Patent number 9,213,666
- Issue date Dec 15, 2015
- Intel Corporation
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common idle state, active state and credit management for an interface
- Patent number 9,122,815
- Issue date Sep 1, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Issuing requests to a fabric
- Patent number 9,075,929
- Issue date Jul 7, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Issuing requests to a fabric
- Patent number 9,064,051
- Issue date Jun 23, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing a sideband message interface for system on a chip (SoC)
- Patent number 9,053,251
- Issue date Jun 9, 2015
- Intel Corporation
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sending packets with expanded headers
- Patent number 8,929,373
- Issue date Jan 6, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing error handling support to legacy devices
- Patent number 8,874,976
- Issue date Oct 28, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common idle state, active state and credit management for an interface
- Patent number 8,805,926
- Issue date Aug 12, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Issuing requests to a fabric
- Patent number 8,775,700
- Issue date Jul 8, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggregating completion messages in a sideband interface
- Patent number 8,711,875
- Issue date Apr 29, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Supporting multiple channels of a single interface
- Patent number 8,713,234
- Issue date Apr 29, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing multiple decode options for a system-on-chip (SoC) fabric
- Patent number 8,713,240
- Issue date Apr 29, 2014
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to merge and align data from distributed memor...
- Patent number 8,370,558
- Issue date Feb 5, 2013
- Intel Corporation
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple multi-threaded processors having an L1 instruction cache a...
- Patent number 8,087,024
- Issue date Dec 27, 2011
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scalable, high-performance, global interconnect scheme for multi-th...
- Patent number 7,707,266
- Issue date Apr 27, 2010
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with bank sorting and scheduling
- Patent number 7,698,498
- Issue date Apr 13, 2010
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two stage queue arbitration
- Patent number 7,653,069
- Issue date Jan 26, 2010
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Thread-based engine cache partitioning
- Patent number 7,536,692
- Issue date May 19, 2009
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for two-stage packet classification using most...
- Patent number 7,525,958
- Issue date Apr 28, 2009
- Intel Corporation
- Alok Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for a high efficiency two-stage rotating prior...
- Patent number 7,512,729
- Issue date Mar 31, 2009
- Intel Corporation
- Bijoy Bose
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus to support efficient check-point and role-back...
- Patent number 7,505,410
- Issue date Mar 17, 2009
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Heterogeneous ML Accelerator Cluster with Flexible System Resource...
- Publication number 20240231667
- Publication date Jul 11, 2024
- Google LLC
- Sheng Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR HANDLING NON-POSTED MEMORY WRITE T...
- Publication number 20210042147
- Publication date Feb 11, 2021
- Intel Corporation
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR HANDLING NON-POSTED MEMORY WRITE T...
- Publication number 20180181432
- Publication date Jun 28, 2018
- Intel Corporation
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE
- Publication number 20160132447
- Publication date May 12, 2016
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ULTRA LOW POWER ARCHITECTURE TO SUPPORT ALWAYS ON PATH TO MEMORY
- Publication number 20160019936
- Publication date Jan 21, 2016
- Suketu R. Partiwala
- G11 - INFORMATION STORAGE
Information Patent Application
Issuing Requests To A Fabric
- Publication number 20150113189
- Publication date Apr 23, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENDING PACKETS WITH EXPANDED HEADERS
- Publication number 20150092779
- Publication date Apr 2, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Providing Error Handling Support To Legacy Devices
- Publication number 20150067412
- Publication date Mar 5, 2015
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing A Sideband Message Interface For System On A Chip (SoC)
- Publication number 20150019788
- Publication date Jan 15, 2015
- Intel Corporation
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Common Idle State, Active State And Credit Management For An Interface
- Publication number 20150012681
- Publication date Jan 8, 2015
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Issuing Requests To A Fabric
- Publication number 20140289435
- Publication date Sep 25, 2014
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing Multiple Decode Options For A System-On-Chip (SoC) Fabric
- Publication number 20140258583
- Publication date Sep 11, 2014
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE
- Publication number 20140258492
- Publication date Sep 11, 2014
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Supporting Multiple Channels Of A Single Interface
- Publication number 20140258578
- Publication date Sep 11, 2014
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing A Sideband Message Interface For System On A Chip (SoC)
- Publication number 20130138858
- Publication date May 30, 2013
- Robert P. Adler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing Error Handling Support To Legacy Devices
- Publication number 20130086433
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Providing Multiple Decode Options For A System-On-Chip (SoC) Fabric
- Publication number 20130086296
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Aggregating Completion Messages In A Sideband Interface
- Publication number 20130083794
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Common Idle State, Active State And Credit Management For An Interface
- Publication number 20130086139
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Supporting Multiple Channels Of A Single Interface
- Publication number 20130086288
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Issuing Requests To A Fabric
- Publication number 20130086586
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sending Packets With Expanded Headers
- Publication number 20130083798
- Publication date Apr 4, 2013
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO MERGE AND ALIGN DATA FROM DISTRIBUTED MEMOR...
- Publication number 20090132773
- Publication date May 21, 2009
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple multi-threaded processors having an L1 instruction cache a...
- Publication number 20090089546
- Publication date Apr 2, 2009
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller with bank sorting and scheduling
- Publication number 20070156946
- Publication date Jul 5, 2007
- Intel Corporation
- Sridhar Lakshmanamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Two stage queue arbitration
- Publication number 20070153803
- Publication date Jul 5, 2007
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
On-device packet descriptor cache
- Publication number 20070153818
- Publication date Jul 5, 2007
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Managing on-chip queues in switched fabric networks
- Publication number 20070140282
- Publication date Jun 21, 2007
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Instruction-assisted cache management for efficient use of cache an...
- Publication number 20070079073
- Publication date Apr 5, 2007
- Mark Rosenbluth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to support efficient check-point and role-back...
- Publication number 20070008985
- Publication date Jan 11, 2007
- Sridhar Lakshmanamurthy
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Sridhar Lakshmanamurthy

Person

Patents Grantslast 30 patents

Method, apparatus and system for handling non-posted memory write t...

Method, apparatus and system for handling non-posted memory write t...

Sending packets with expanded headers

Ultra low power architecture to support always on path to memory

Systems and an apparatus with a sideband interface interconnecting...

Providing multiple decode options for a system-on-chip (SoC) fabric

Supporting multiple channels of a single interface

Providing error handling support to legacy devices

Aggregating completion messages in a sideband interface

Providing a sideband message interface for system on a chip (SoC)

Common idle state, active state and credit management for an interface

Issuing requests to a fabric

Issuing requests to a fabric

Providing a sideband message interface for system on a chip (SoC)

Sending packets with expanded headers

Providing error handling support to legacy devices

Common idle state, active state and credit management for an interface

Issuing requests to a fabric

Aggregating completion messages in a sideband interface

Supporting multiple channels of a single interface

Providing multiple decode options for a system-on-chip (SoC) fabric

Apparatus and method to merge and align data from distributed memor...

Multiple multi-threaded processors having an L1 instruction cache a...

Scalable, high-performance, global interconnect scheme for multi-th...

Memory controller with bank sorting and scheduling

Two stage queue arbitration

Thread-based engine cache partitioning

Apparatus and method for two-stage packet classification using most...

Method and apparatus for a high efficiency two-stage rotating prior...

Method and apparatus to support efficient check-point and role-back...

Patents Applicationslast 30 patents

Heterogeneous ML Accelerator Cluster with Flexible System Resource...

METHOD, APPARATUS AND SYSTEM FOR HANDLING NON-POSTED MEMORY WRITE T...

METHOD, APPARATUS AND SYSTEM FOR HANDLING NON-POSTED MEMORY WRITE T...

AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE

ULTRA LOW POWER ARCHITECTURE TO SUPPORT ALWAYS ON PATH TO MEMORY

Issuing Requests To A Fabric

SENDING PACKETS WITH EXPANDED HEADERS

Providing Error Handling Support To Legacy Devices

Providing A Sideband Message Interface For System On A Chip (SoC)

Common Idle State, Active State And Credit Management For An Interface

Issuing Requests To A Fabric

Providing Multiple Decode Options For A System-On-Chip (SoC) Fabric

AGGREGATING COMPLETION MESSAGES IN A SIDEBAND INTERFACE

Supporting Multiple Channels Of A Single Interface

Providing A Sideband Message Interface For System On A Chip (SoC)

Providing Error Handling Support To Legacy Devices

Providing Multiple Decode Options For A System-On-Chip (SoC) Fabric

Aggregating Completion Messages In A Sideband Interface

Common Idle State, Active State And Credit Management For An Interface

Supporting Multiple Channels Of A Single Interface

Issuing Requests To A Fabric

Sending Packets With Expanded Headers

APPARATUS AND METHOD TO MERGE AND ALIGN DATA FROM DISTRIBUTED MEMOR...

Multiple multi-threaded processors having an L1 instruction cache a...

Memory controller with bank sorting and scheduling

Two stage queue arbitration

On-device packet descriptor cache

Managing on-chip queues in switched fabric networks

Instruction-assisted cache management for efficient use of cache an...

Method and apparatus to support efficient check-point and role-back...