Sridhar Samudrala

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Extension of openvswitch megaflow offloads to hardware to address h...
- Patent number 12,231,339
- Issue date Feb 18, 2025
- Intel Corporation
- Namrata Limaye
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Technologies that provide policy enforcement for resource access
- Patent number 12,170,624
- Issue date Dec 17, 2024
- Intel Corporation
- Anjali Singhai Jain
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 12,086,594
- Issue date Sep 10, 2024
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 11,740,904
- Issue date Aug 29, 2023
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 11,210,096
- Issue date Dec 28, 2021
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 10,795,680
- Issue date Oct 6, 2020
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual group policy based filtering within an overlay network
- Patent number 10,135,687
- Issue date Nov 20, 2018
- Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
- Vivek Kashyap
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Instruction and logic to provide vector blend and permute functiona...
- Patent number 10,037,205
- Issue date Jul 31, 2018
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double rounded combined floating-point multiply and add
- Patent number 9,778,909
- Issue date Oct 3, 2017
- Intel Corporation
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector friendly instruction format and execution thereof
- Patent number 9,513,917
- Issue date Dec 6, 2016
- Intel Corporation
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double rounded combined floating-point multiply and add
- Patent number 9,477,441
- Issue date Oct 25, 2016
- Intel Corporation
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined floating point multiplier adder with intermediate rounding...
- Patent number 9,389,871
- Issue date Jul 12, 2016
- Intel Corporation
- Marc Lupon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for facilitating dynamic and efficient fusion of computin...
- Patent number 9,329,848
- Issue date May 3, 2016
- Intel Corporation
- Marc Lupon
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Double rounded combined floating-point multiply and add
- Patent number 9,213,523
- Issue date Dec 15, 2015
- Intel Corporation
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector logical reduction operation implemented using swizzling on a...
- Patent number 9,141,386
- Issue date Sep 22, 2015
- Intel Corporation
- Jeff Wiedemeier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional unit for vector leading zeroes, vector trailing zeroes,...
- Patent number 9,092,213
- Issue date Jul 28, 2015
- Intel Corporation
- Jeff Wiedemeier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional unit for vector integer multiply add instruction
- Patent number 8,667,042
- Issue date Mar 4, 2014
- Intel Corporation
- Jeff Wiedemeier
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20240427600
- Publication date Dec 26, 2024
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O ACCELERATION IN A MULTI-NODE ARCHITECTURE
- Publication number 20240126622
- Publication date Apr 18, 2024
- Anil Vasudevan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20240061683
- Publication date Feb 22, 2024
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20220129274
- Publication date Apr 28, 2022
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES THAT PROVIDE POLICY ENFORCEMENT FOR RESOURCE ACCESS
- Publication number 20220029929
- Publication date Jan 27, 2022
- Intel Corporation
- Anjali Singhai JAIN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
QUEUE SCALING BASED, AT LEAST, IN PART, ON PROCESSING LOAD
- Publication number 20210326177
- Publication date Oct 21, 2021
- Intel Corporation
- Anil VASUDEVAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENSION OF OPENVSWITCH MEGAFLOW OFFLOADS TO HARDWARE TO ADDRESS H...
- Publication number 20210144094
- Publication date May 13, 2021
- Namrata Limaye
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20200394042
- Publication date Dec 17, 2020
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR INTERRUPT DISASSOCIATED QUEUING FOR MULTI-QUEUE I/...
- Publication number 20190391940
- Publication date Dec 26, 2019
- Intel Corporation
- Anil Vasudevan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20190227800
- Publication date Jul 25, 2019
- Intel Corporation
- Robert C. VALENTINE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS...
- Publication number 20190108029
- Publication date Apr 11, 2019
- Intel Corporation
- Jesus CORBAL SAN ADRIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS...
- Publication number 20190108030
- Publication date Apr 11, 2019
- Intel Corporation
- Jesus CORBAL SAN ADRIAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for a Field Programmable Gate Array to Perform a Functio...
- Publication number 20180150654
- Publication date May 31, 2018
- Intel Corporation
- Patrick Connor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD
- Publication number 20170039033
- Publication date Feb 9, 2017
- Intel Corporation
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD
- Publication number 20160077802
- Publication date Mar 17, 2016
- Intel Corporation
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL GROUP POLICY BASED FILTERING WITHIN AN OVERLAY NETWORK
- Publication number 20150195137
- Publication date Jul 9, 2015
- Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
- VIVEK KASHYAP
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT FUSION OF COMPUTIN...
- Publication number 20150026671
- Publication date Jan 22, 2015
- Marc Lupon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC TO PROVIDE VECTOR BLEND AND PERMUTE FUNCTIONA...
- Publication number 20140372727
- Publication date Dec 18, 2014
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINED FLOATING POINT MULTIPLIER ADDER WITH INTERMEDIATE ROUNDING...
- Publication number 20140281419
- Publication date Sep 18, 2014
- Intel Corporation
- Marc Lupon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20140149724
- Publication date May 29, 2014
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD
- Publication number 20140006467
- Publication date Jan 2, 2014
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CONTROLLING A MXCSR
- Publication number 20130326199
- Publication date Dec 5, 2013
- Grigorios Magklis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
- Publication number 20130305020
- Publication date Nov 14, 2013
- Robert C. Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS...
- Publication number 20120254588
- Publication date Oct 4, 2012
- Jesus Corbal San Adrian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INT...
- Publication number 20120254592
- Publication date Oct 4, 2012
- Jesus Corbal San Adrian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL UNIT FOR VECTOR LEADING ZEROES, VECTOR TRAILING ZEROES,...
- Publication number 20120079253
- Publication date Mar 29, 2012
- Jeff Wiedemeier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL UNIT FOR VECTOR INTEGER MULTIPLY ADD INSTRUCTION
- Publication number 20120078992
- Publication date Mar 29, 2012
- Jeff Wiedemeier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods, Systems and Computer Program Products for Dynamic Selectio...
- Publication number 20090316581
- Publication date Dec 24, 2009
- International Business Machines Corporation
- Vivek Kashyap
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Sridhar Samudrala

Person

Patents Grantslast 30 patents

Extension of openvswitch megaflow offloads to hardware to address h...

Technologies that provide policy enforcement for resource access

Vector friendly instruction format and execution thereof

Vector friendly instruction format and execution thereof

Vector friendly instruction format and execution thereof

Vector friendly instruction format and execution thereof

Virtual group policy based filtering within an overlay network

Instruction and logic to provide vector blend and permute functiona...

Double rounded combined floating-point multiply and add

Vector friendly instruction format and execution thereof

Double rounded combined floating-point multiply and add

Combined floating point multiplier adder with intermediate rounding...

Mechanism for facilitating dynamic and efficient fusion of computin...

Double rounded combined floating-point multiply and add

Vector logical reduction operation implemented using swizzling on a...

Functional unit for vector leading zeroes, vector trailing zeroes,...

Functional unit for vector integer multiply add instruction

Patents Applicationslast 30 patents

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

I/O ACCELERATION IN A MULTI-NODE ARCHITECTURE

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

TECHNOLOGIES THAT PROVIDE POLICY ENFORCEMENT FOR RESOURCE ACCESS

QUEUE SCALING BASED, AT LEAST, IN PART, ON PROCESSING LOAD

EXTENSION OF OPENVSWITCH MEGAFLOW OFFLOADS TO HARDWARE TO ADDRESS H...

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

TECHNOLOGIES FOR INTERRUPT DISASSOCIATED QUEUING FOR MULTI-QUEUE I/...

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS...

SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS...

Techniques for a Field Programmable Gate Array to Perform a Functio...

DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD

DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD

VIRTUAL GROUP POLICY BASED FILTERING WITHIN AN OVERLAY NETWORK

MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT FUSION OF COMPUTIN...

INSTRUCTION AND LOGIC TO PROVIDE VECTOR BLEND AND PERMUTE FUNCTIONA...

COMBINED FLOATING POINT MULTIPLIER ADDER WITH INTERMEDIATE ROUNDING...

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD

METHOD AND APPARATUS FOR CONTROLLING A MXCSR

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS...

SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INT...

FUNCTIONAL UNIT FOR VECTOR LEADING ZEROES, VECTOR TRAILING ZEROES,...

FUNCTIONAL UNIT FOR VECTOR INTEGER MULTIPLY ADD INSTRUCTION

Methods, Systems and Computer Program Products for Dynamic Selectio...