Srinivas Patil

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
On-chip clock controller (OCC) manager based turbo capture clocking
- Patent number 11,237,587
- Issue date Feb 1, 2022
- QUALCOMM Incorporated
- Punit Kishore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Laser-based integrated circuit testing techniques
- Patent number 10,324,131
- Issue date Jun 18, 2019
- QUALCOMM Incorporated
- Lesly Endrinal
- G01 - MEASURING TESTING
Information Patent Grant
Functional fabric based test access mechanism for SoCs
- Patent number 9,087,037
- Issue date Jul 21, 2015
- Intel Corporation
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional fabric based test wrapper for circuit testing of IP blocks
- Patent number 9,043,665
- Issue date May 26, 2015
- Intel Corporation
- Srinivas Patil
- G01 - MEASURING TESTING
Information Patent Grant
Functional fabric-based test controller for functional and structur...
- Patent number 8,793,095
- Issue date Jul 29, 2014
- Intel Corporation
- Srinivas Patil
- G01 - MEASURING TESTING
Information Patent Grant
Functional fabric based test access mechanism for SoCs
- Patent number 8,522,189
- Issue date Aug 27, 2013
- Intel Corporation
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, system, and method for optimized concurrent error detection
- Patent number 7,861,116
- Issue date Dec 28, 2010
- Intel Corporation
- Abhijit Jas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible scan architecture
- Patent number 7,216,274
- Issue date May 8, 2007
- Intel Corporation
- Talal K. Jaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Weight compression/decompression system
- Patent number 7,197,721
- Issue date Mar 27, 2007
- Intel Corporation
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Linear feedback shift register reseeding
- Patent number 7,155,648
- Issue date Dec 26, 2006
- Intel Corporation
- Abhijit Jas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for creating testable circuit designs having e...
- Patent number 6,456,961
- Issue date Sep 24, 2002
- Srinivas Patil
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for testing self-timed circuitry
- Patent number 5,912,900
- Issue date Jun 15, 1999
- International Business Machines Corporation
- Christopher McCall Durham
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for testing self-timed circuitry
- Patent number 5,870,411
- Issue date Feb 9, 1999
- International Business Machines Corporation
- Christopher McCall Durham
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
FUNCTIONAL FABRIC BASED TEST ACCESS MECHANISM FOR SOCS
- Publication number 20130268808
- Publication date Oct 10, 2013
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL FABRIC-BASED TEST CONTROLLER FOR FUNCTIONAL AND STRUCTUR...
- Publication number 20120232825
- Publication date Sep 13, 2012
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL FABRIC BASED TEST ACCESS MECHANISM FOR SOCS
- Publication number 20120233504
- Publication date Sep 13, 2012
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FUNCTIONAL FABRIC BASED TEST WRAPPER FOR CIRCUIT TESTING OF IP BLOCKS
- Publication number 20120233514
- Publication date Sep 13, 2012
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE, SYSTEM, AND METHOD FOR OPTIMIZED CONCURRENT ERROR DETECTION
- Publication number 20090172529
- Publication date Jul 2, 2009
- Intel Corporation
- Abhijit Jas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flexible scan architecture
- Publication number 20070168767
- Publication date Jul 19, 2007
- Talal K. Jaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Linear feedback shift register reseeding
- Publication number 20050066244
- Publication date Mar 24, 2005
- Intel Corporation
- Abhijit Jas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flexible scan architecture
- Publication number 20040267504
- Publication date Dec 30, 2004
- Talal K. Jaber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Weight compression/decompression system
- Publication number 20040117710
- Publication date Jun 17, 2004
- Srinivas Patil
- G06 - COMPUTING CALCULATING COUNTING

Srinivas Patil

Person

Patents Grantslast 30 patents

On-chip clock controller (OCC) manager based turbo capture clocking

Laser-based integrated circuit testing techniques

Functional fabric based test access mechanism for SoCs

Functional fabric based test wrapper for circuit testing of IP blocks

Functional fabric-based test controller for functional and structur...

Functional fabric based test access mechanism for SoCs

Device, system, and method for optimized concurrent error detection

Flexible scan architecture

Weight compression/decompression system

Linear feedback shift register reseeding

Method and apparatus for creating testable circuit designs having e...

Method and system for testing self-timed circuitry

Method and system for testing self-timed circuitry

Patents Applicationslast 30 patents

FUNCTIONAL FABRIC BASED TEST ACCESS MECHANISM FOR SOCS

FUNCTIONAL FABRIC-BASED TEST CONTROLLER FOR FUNCTIONAL AND STRUCTUR...

FUNCTIONAL FABRIC BASED TEST ACCESS MECHANISM FOR SOCS

FUNCTIONAL FABRIC BASED TEST WRAPPER FOR CIRCUIT TESTING OF IP BLOCKS

DEVICE, SYSTEM, AND METHOD FOR OPTIMIZED CONCURRENT ERROR DETECTION

Flexible scan architecture

Linear feedback shift register reseeding

Flexible scan architecture

Weight compression/decompression system