Srinivas Perisetty

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and methods for on-die temperature sensing to improve FPG...
- Patent number 10,200,037
- Issue date Feb 5, 2019
- Altera Corporation
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and methods for on-die temperature sensing to improve FPG...
- Patent number 9,735,779
- Issue date Aug 15, 2017
- Altera Corporation
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuits with asymmetric and stacked transistors
- Patent number 9,496,268
- Issue date Nov 15, 2016
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits with asymmetric and stacked transistors
- Patent number 8,750,026
- Issue date Jun 10, 2014
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods for power management in integrated circuits
- Patent number 8,732,635
- Issue date May 20, 2014
- Altera Corporation
- David Lewis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory elements with increased write margin and soft error upset im...
- Patent number 8,711,614
- Issue date Apr 29, 2014
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-biased voltage regulation circuitry for memory
- Patent number 8,618,786
- Issue date Dec 31, 2013
- Altera Corporation
- Srinivas Perisetty
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits with asymmetric and stacked transistors
- Patent number 8,482,963
- Issue date Jul 9, 2013
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random-access memory with boosted voltages
- Patent number 8,279,660
- Issue date Oct 2, 2012
- Altera Corporation
- Srinivas Perisetty
- G11 - INFORMATION STORAGE
Information Patent Grant
Performance improvements in an integrated circuit by selectively ap...
- Patent number 8,099,704
- Issue date Jan 17, 2012
- Altera Corporation
- Srinivas Perisetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electrostatic discharge protection in a field programmable gate array
- Patent number 7,990,664
- Issue date Aug 2, 2011
- Altera Corporation
- Srinivas Perisetty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge protection circuitry
- Patent number 7,978,450
- Issue date Jul 12, 2011
- Altera Corporation
- Srinivas Perisetty
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Static random-access memory with boosted voltages
- Patent number 7,957,177
- Issue date Jun 7, 2011
- Altera Corporation
- Srinivas Perisetty
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory elements with increased write margin and soft error upset im...
- Patent number 7,920,410
- Issue date Apr 5, 2011
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable-output current-load-independent negative-voltage regulator
- Patent number 7,863,968
- Issue date Jan 4, 2011
- Altera Corporation
- Srinivas Perisetty
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method and apparatus for providing electrostatic discharge protecti...
- Patent number 7,782,581
- Issue date Aug 24, 2010
- Altera Corporation
- Srinivas Perisetty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits with adjustable body bias and power supply circ...
- Patent number 7,675,317
- Issue date Mar 9, 2010
- Altera Corporation
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit voltage regulator
- Patent number 7,639,067
- Issue date Dec 29, 2009
- Altera Corporation
- Srinivas Perisetty
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Hotsocket-compatible body bias circuitry with power-up current redu...
- Patent number 7,639,041
- Issue date Dec 29, 2009
- Altera Corporation
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Booster circuit with capacitor protection circuitry
- Patent number 7,629,831
- Issue date Dec 8, 2009
- Altera Corporation
- Srinivas Perisetty
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Adjustable transistor body bias circuitry
- Patent number 7,592,832
- Issue date Sep 22, 2009
- Altera Corporation
- Srinivas Perisetty
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Testing circuitry for programmable logic devices with selectable po...
- Patent number 7,571,413
- Issue date Aug 4, 2009
- Altera Corporation
- Jayabrata Ghosh Dastidar
- G01 - MEASURING TESTING
Information Patent Grant
Adjustable transistor body bias generation circuitry with latch-up...
- Patent number 7,514,953
- Issue date Apr 7, 2009
- Altera Corporation
- Srinivas Perisetty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ESD protection structure
- Patent number 7,511,932
- Issue date Mar 31, 2009
- Altera Corporation
- Antonio Gallerano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Latch-up prevention circuitry for integrated circuits with transist...
- Patent number 7,501,849
- Issue date Mar 10, 2009
- Altera Corporation
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adjustable transistor body bias circuitry
- Patent number 7,495,471
- Issue date Feb 24, 2009
- Altera Corporation
- Srinivas Perisetty
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Apparatus and methods for power management in integrated circuits
- Patent number 7,405,589
- Issue date Jul 29, 2008
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch-up prevention circuitry for integrated circuits with transist...
- Patent number 7,355,437
- Issue date Apr 8, 2008
- Altera Corporation
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adjustable transistor body bias generation circuitry with latch-up...
- Patent number 7,330,049
- Issue date Feb 12, 2008
- Altera Corporation
- Srinivas Perisetty
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHODS FOR ON-DIE TEMPERATURE SENSING TO IMPROVE FPG...
- Publication number 20170373690
- Publication date Dec 28, 2017
- Altera Corporation
- Srinivas Perisetty
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated Circuits with Asymmetric and Stacked Transistors
- Publication number 20160232952
- Publication date Aug 11, 2016
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuits with Asymmetric and Stacked Transistors
- Publication number 20150318029
- Publication date Nov 5, 2015
- Altera Corporation
- Jun Liu
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS
- Publication number 20140258956
- Publication date Sep 11, 2014
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC RANDOM-ACCESS MEMORY WITH BOOSTED VOLTAGES
- Publication number 20110211384
- Publication date Sep 1, 2011
- Srinivas Perisetty
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM-ACCESS MEMORY WITH BOOSTED VOLTAGES
- Publication number 20090303826
- Publication date Dec 10, 2009
- Srinivas Perisetty
- G11 - INFORMATION STORAGE
Information Patent Application
Varactor-based charge pump
- Publication number 20090072891
- Publication date Mar 19, 2009
- Srinivas Perisetty
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Integrated circuits with adjustable body bias and power supply circ...
- Publication number 20090072857
- Publication date Mar 19, 2009
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS
- Publication number 20080263481
- Publication date Oct 23, 2008
- Altera Corporation
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTABLE TRANSISTOR BODY BIAS CIRCUITRY
- Publication number 20080258802
- Publication date Oct 23, 2008
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LATCH-UP PREVENTION CIRCUITRY FOR INTEGRATED CIRCUITS WITH TRANSIST...
- Publication number 20080150575
- Publication date Jun 26, 2008
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADJUSTABLE TRANSISTOR BODY BIAS GENERATION CIRCUITRY WITH LATCH-UP...
- Publication number 20080094100
- Publication date Apr 24, 2008
- Altera Corporation
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustable transistor body bias circuitry
- Publication number 20070205824
- Publication date Sep 6, 2007
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADJUSTABLE TRANSISTOR BODY BIAS GENERATION CIRCUITRY WITH LATCH-UP...
- Publication number 20070205802
- Publication date Sep 6, 2007
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Latch-up prevention circuitry for integrated circuits with transist...
- Publication number 20070205801
- Publication date Sep 6, 2007
- Srinivas Perisetty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and methods for power management in integrated circuits
- Publication number 20070040576
- Publication date Feb 22, 2007
- David Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Redundant column read in a memory array
- Publication number 20070022330
- Publication date Jan 25, 2007
- Srinivas Perisetty
- G11 - INFORMATION STORAGE

Srinivas Perisetty

Person

Patents Grantslast 30 patents

Apparatus and methods for on-die temperature sensing to improve FPG...

Apparatus and methods for on-die temperature sensing to improve FPG...

Integrated circuits with asymmetric and stacked transistors

Integrated circuits with asymmetric and stacked transistors

Apparatus and methods for power management in integrated circuits

Memory elements with increased write margin and soft error upset im...

Self-biased voltage regulation circuitry for memory

Integrated circuits with asymmetric and stacked transistors

Static random-access memory with boosted voltages

Performance improvements in an integrated circuit by selectively ap...

Electrostatic discharge protection in a field programmable gate array

Electrostatic discharge protection circuitry

Static random-access memory with boosted voltages

Memory elements with increased write margin and soft error upset im...

Variable-output current-load-independent negative-voltage regulator

Method and apparatus for providing electrostatic discharge protecti...

Integrated circuits with adjustable body bias and power supply circ...

Integrated circuit voltage regulator

Hotsocket-compatible body bias circuitry with power-up current redu...

Booster circuit with capacitor protection circuitry

Adjustable transistor body bias circuitry

Testing circuitry for programmable logic devices with selectable po...

Adjustable transistor body bias generation circuitry with latch-up...

ESD protection structure

Latch-up prevention circuitry for integrated circuits with transist...

Adjustable transistor body bias circuitry

Apparatus and methods for power management in integrated circuits

Latch-up prevention circuitry for integrated circuits with transist...

Adjustable transistor body bias generation circuitry with latch-up...

Patents Applicationslast 30 patents

APPARATUS AND METHODS FOR ON-DIE TEMPERATURE SENSING TO IMPROVE FPG...

Integrated Circuits with Asymmetric and Stacked Transistors

Integrated Circuits with Asymmetric and Stacked Transistors

APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS

STATIC RANDOM-ACCESS MEMORY WITH BOOSTED VOLTAGES

STATIC RANDOM-ACCESS MEMORY WITH BOOSTED VOLTAGES

Varactor-based charge pump

Integrated circuits with adjustable body bias and power supply circ...

APPARATUS AND METHODS FOR POWER MANAGEMENT IN INTEGRATED CIRCUITS

ADJUSTABLE TRANSISTOR BODY BIAS CIRCUITRY

LATCH-UP PREVENTION CIRCUITRY FOR INTEGRATED CIRCUITS WITH TRANSIST...

ADJUSTABLE TRANSISTOR BODY BIAS GENERATION CIRCUITRY WITH LATCH-UP...

Adjustable transistor body bias circuitry

ADJUSTABLE TRANSISTOR BODY BIAS GENERATION CIRCUITRY WITH LATCH-UP...

Latch-up prevention circuitry for integrated circuits with transist...

Apparatus and methods for power management in integrated circuits

Redundant column read in a memory array