Srinivasan Dasasathyan

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-resource aware partitioning for integrated circuits
- Patent number 8,473,881
- Issue date Jun 25, 2013
- Xilinx, Inc.
- Wei Mark Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing sub-circuits with predictable behavior within a circui...
- Patent number 8,448,122
- Issue date May 21, 2013
- Xilinx, Inc.
- Vishal Suthar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routability based placement for multi-die integrated circuits
- Patent number 8,418,115
- Issue date Apr 9, 2013
- Xilinx, Inc.
- Marvin Tom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of placing input/output blocks on an integrated circuit device
- Patent number 8,312,405
- Issue date Nov 13, 2012
- Xilinx, Inc.
- Victor Slonim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control set constraint driven force directed analytical placer for...
- Patent number 8,230,377
- Issue date Jul 24, 2012
- Xilinx, Inc.
- Wei Mark Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of and system for placing clock circuits in an integrated ci...
- Patent number 8,225,262
- Issue date Jul 17, 2012
- Xilinx, Inc.
- Marvin Tom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock domain partitioning of programmable integrated circuits
- Patent number 8,091,060
- Issue date Jan 3, 2012
- Xilinx, Inc.
- Marvin Tom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of estimating net delays in tile-based PLD architectures
- Patent number 7,735,039
- Issue date Jun 8, 2010
- Xilinx, Inc.
- Srinivasan Dasasathyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cost-based performance driven legalization technique for placement...
- Patent number 7,636,876
- Issue date Dec 22, 2009
- Xilinx, Inc.
- Sankaranarayanan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of input/output blocks of an electronic design in an inte...
- Patent number 7,392,499
- Issue date Jun 24, 2008
- Xilinx, Inc.
- Guenter Stenz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method system and apparatus for floorplanning programmable logic de...
- Patent number 7,313,778
- Issue date Dec 25, 2007
- Xilinx, Inc.
- Guenter Stenz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated local clock placement for FPGA designs
- Patent number 7,240,315
- Issue date Jul 3, 2007
- Xilinx, Inc.
- Qiang Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for incremental design in programmabl...
- Patent number 7,149,993
- Issue date Dec 12, 2006
- Xilinx, Inc.
- Rajat Aggarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated clock and input output placer
- Patent number 7,149,994
- Issue date Dec 12, 2006
- Xilinx, Inc.
- Srinivasan Dasasathyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for application of network flow techniques under constraints
- Patent number 7,143,380
- Issue date Nov 28, 2006
- Xilinx, Inc.
- Jason H. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of objects with partial shape restriction
- Patent number 6,857,115
- Issue date Feb 15, 2005
- Xilinx, Inc.
- Srinivasan Dasasathyan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of clock objects under constraints
- Patent number 6,789,244
- Issue date Sep 7, 2004
- Xilinx, Inc.
- Srinivasan Dasasathyan
- G06 - COMPUTING CALCULATING COUNTING

Srinivasan Dasasathyan

Person

Patents Grantslast 30 patents

Multi-resource aware partitioning for integrated circuits

Implementing sub-circuits with predictable behavior within a circui...

Routability based placement for multi-die integrated circuits

Method of placing input/output blocks on an integrated circuit device

Control set constraint driven force directed analytical placer for...

Method of and system for placing clock circuits in an integrated ci...

Clock domain partitioning of programmable integrated circuits

Methods of estimating net delays in tile-based PLD architectures

Cost-based performance driven legalization technique for placement...

Placement of input/output blocks of an electronic design in an inte...

Method system and apparatus for floorplanning programmable logic de...

Automated local clock placement for FPGA designs

Method, system, and apparatus for incremental design in programmabl...

Integrated clock and input output placer

Method for application of network flow techniques under constraints

Placement of objects with partial shape restriction

Placement of clock objects under constraints