Sriram NATARAJAN

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Firmware management of least recently used memory for cache hint op...
- Patent number 12,141,077
- Issue date Nov 12, 2024
- SK Hynix NAND Product Solutions Corp.
- Sriram Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling memory overhead for storing integrity data in solid sta...
- Patent number 12,118,222
- Issue date Oct 15, 2024
- SK Hynix NAND Product Solutions Corp.
- Arun Athreya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for preventing read disturb in NAND memory
- Patent number 12,094,545
- Issue date Sep 17, 2024
- INTEL NDTM US LLC
- Arun Sitaram Athreya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for preventing read disturb in NAND memory
- Patent number 11,769,557
- Issue date Sep 26, 2023
- Intel Corporation
- Arun Sitaram Athreya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System approach to reduce stable threshold voltage (Vt) read distur...
- Patent number 11,302,405
- Issue date Apr 12, 2022
- Intel Corporation
- Sriram Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detection and error-handling of high error rate blocks during copyback
- Patent number 11,145,389
- Issue date Oct 12, 2021
- Intel Corporation
- Shankar Natarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic single level cell memory controller
- Patent number 11,119,672
- Issue date Sep 14, 2021
- Intel Corporation
- Shankar Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mass storage device with host initiated buffer flushing
- Patent number 10,877,686
- Issue date Dec 29, 2020
- Intel Corporation
- Shankar Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block management for dynamic single-level cell buffers in storage d...
- Patent number 10,650,886
- Issue date May 12, 2020
- Intel Corporation
- Shankar Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host managed solid state drivecaching using dynamic write acceleration
- Patent number 10,379,782
- Issue date Aug 13, 2019
- Intel Corporation
- Suresh Nagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block management for dynamic single-level cell buffers in storage d...
- Patent number 10,229,735
- Issue date Mar 12, 2019
- Intel Corporation
- Shankar Natarajan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CONTROLLING MEMORY OVERHEAD FOR STORING INTEGRITY DATA IN SOLID STA...
- Publication number 20250021255
- Publication date Jan 16, 2025
- SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Arun ATHREYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FIRMWARE MANAGEMENT OF LEAST RECENTLY USED MEMORY FOR CACHE HINT OP...
- Publication number 20250021489
- Publication date Jan 16, 2025
- SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Sriram NATARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST BANDWIDTH OPTIMIZED DATA STREAM MEMORY WRITES
- Publication number 20240394193
- Publication date Nov 28, 2024
- SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Shankar Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING MEMORY OVERHEAD FOR STORING INTEGRITY DATA IN SOLID STA...
- Publication number 20240289040
- Publication date Aug 29, 2024
- SK Hynix NAND Product Solutions Corp. (dba Solidigm)
- Arun ATHREYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR PREVENTING READ DISTURB IN NAND MEMORY
- Publication number 20230395166
- Publication date Dec 7, 2023
- Intel Corporation
- Arun Sitaram ATHREYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC SINGLE LEVEL CELL MEMORY CONTROLLER
- Publication number 20200167089
- Publication date May 28, 2020
- Intel Corporation
- Shankar Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR PREVENTING READ DISTURB IN NAND MEMORY
- Publication number 20200118636
- Publication date Apr 16, 2020
- Intel Corporation
- Arun Sitaram ATHREYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM APPROACH TO REDUCE STABLE THRESHOLD VOLTAGE (VT) READ DISTUR...
- Publication number 20200118637
- Publication date Apr 16, 2020
- Intel Corporation
- Sriram NATARAJAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTION AND ERROR-HANDLING OF HIGH ERROR RATE BLOCKS DURING COPYBACK
- Publication number 20200105363
- Publication date Apr 2, 2020
- Intel Corporation
- Shankar Natarajan
- G11 - INFORMATION STORAGE
Information Patent Application
Block Management for Dynamic Single-Level Cell Buffers in Storage D...
- Publication number 20190267080
- Publication date Aug 29, 2019
- Intel Corporation
- Shankar Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST MANAGED SOLID STATE DRIVECACHING USING DYNAMIC WRITE ACCELERATION
- Publication number 20190056886
- Publication date Feb 21, 2019
- Intel Corporation
- Suresh Nagarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MASS STORAGE DEVICE WITH HOST INITIATED BUFFER FLUSHING
- Publication number 20190042140
- Publication date Feb 7, 2019
- Intel Corporation
- Shankar NATARAJAN
- G06 - COMPUTING CALCULATING COUNTING

Sriram NATARAJAN

Person

Patents Grantslast 30 patents

Firmware management of least recently used memory for cache hint op...

Controlling memory overhead for storing integrity data in solid sta...

Techniques for preventing read disturb in NAND memory

Techniques for preventing read disturb in NAND memory

System approach to reduce stable threshold voltage (Vt) read distur...

Detection and error-handling of high error rate blocks during copyback

Dynamic single level cell memory controller

Mass storage device with host initiated buffer flushing

Block management for dynamic single-level cell buffers in storage d...

Host managed solid state drivecaching using dynamic write acceleration

Block management for dynamic single-level cell buffers in storage d...

Patents Applicationslast 30 patents

CONTROLLING MEMORY OVERHEAD FOR STORING INTEGRITY DATA IN SOLID STA...

FIRMWARE MANAGEMENT OF LEAST RECENTLY USED MEMORY FOR CACHE HINT OP...

HOST BANDWIDTH OPTIMIZED DATA STREAM MEMORY WRITES

CONTROLLING MEMORY OVERHEAD FOR STORING INTEGRITY DATA IN SOLID STA...

TECHNIQUES FOR PREVENTING READ DISTURB IN NAND MEMORY

DYNAMIC SINGLE LEVEL CELL MEMORY CONTROLLER

TECHNIQUES FOR PREVENTING READ DISTURB IN NAND MEMORY

SYSTEM APPROACH TO REDUCE STABLE THRESHOLD VOLTAGE (VT) READ DISTUR...

DETECTION AND ERROR-HANDLING OF HIGH ERROR RATE BLOCKS DURING COPYBACK

Block Management for Dynamic Single-Level Cell Buffers in Storage D...

HOST MANAGED SOLID STATE DRIVECACHING USING DYNAMIC WRITE ACCELERATION

MASS STORAGE DEVICE WITH HOST INITIATED BUFFER FLUSHING