Srivaths Ravi

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Testing of integrated circuits during at-speed mode of operation
- Patent number 11,333,707
- Issue date May 17, 2022
- Texas Instruments Incorporated
- Khushboo Agarwal
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression architecture with bypassable scan chains for low t...
- Patent number 8,856,601
- Issue date Oct 7, 2014
- Texas Instruments Incorporated
- Srivaths Ravi
- G01 - MEASURING TESTING
Information Patent Grant
Circuits and methods for dynamic allocation of scan test resources
- Patent number 8,839,063
- Issue date Sep 16, 2014
- Texas Instruments Incorporated
- Rubin Ajit Parekhji
- G01 - MEASURING TESTING
Information Patent Grant
Low overhead and timing improved architecture for performing error...
- Patent number 8,671,329
- Issue date Mar 11, 2014
- Texas Instruments Incorporated
- Sanjay Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid test compression architecture using multiple codecs for low...
- Patent number 8,527,821
- Issue date Sep 3, 2013
- Texas Instruments Incorporated
- Malav Shrikant Shah
- G01 - MEASURING TESTING
Information Patent Grant
Low overhead and timing improved architecture for performing error...
- Patent number 8,438,344
- Issue date May 7, 2013
- Texas Instruments Incorporated
- Sanjay Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip seed generation using boolean functions for LFSR re-seeding...
- Patent number 8,286,042
- Issue date Oct 9, 2012
- Texas Instruments Incorporated
- Swathi Gangasani
- G01 - MEASURING TESTING
Information Patent Grant
Enhanced control in scan tests of integrated circuits with partitio...
- Patent number 8,205,125
- Issue date Jun 19, 2012
- Texas Instruments Incorporated
- Alan David Hales
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION
- Publication number 20200132763
- Publication date Apr 30, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Khushboo Agarwal
- G01 - MEASURING TESTING
Information Patent Application
TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION
- Publication number 20150212152
- Publication date Jul 30, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Khushboo Agarwal
- G01 - MEASURING TESTING
Information Patent Application
CIRCUITS AND METHODS FOR DYNAMIC ALLOCATION OF SCAN TEST RESOURCES
- Publication number 20140208177
- Publication date Jul 24, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Rubin Ajit Parekhji
- G01 - MEASURING TESTING
Information Patent Application
LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR...
- Publication number 20130246889
- Publication date Sep 19, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Sanjay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan Compression Architecture with Bypassable Scan Chains for Low T...
- Publication number 20130159800
- Publication date Jun 20, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Srivaths Ravi
- G01 - MEASURING TESTING
Information Patent Application
HYBRID TEST COMPRESSION ARCHITECTURE USING MULTIPLE CODECS FOR LOW...
- Publication number 20120304031
- Publication date Nov 29, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Malav Shrikant Shah
- G01 - MEASURING TESTING
Information Patent Application
LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR...
- Publication number 20110225475
- Publication date Sep 15, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Sanjay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIO...
- Publication number 20110099442
- Publication date Apr 28, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Alan David Hales
- G01 - MEASURING TESTING
Information Patent Application
On-Chip Seed Generation Using Boolean Functions for LFSR Re-Seeding...
- Publication number 20100218059
- Publication date Aug 26, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Swathi Gangasani
- G01 - MEASURING TESTING

Srivaths Ravi

Person

Patents Grantslast 30 patents

Testing of integrated circuits during at-speed mode of operation

Scan compression architecture with bypassable scan chains for low t...

Circuits and methods for dynamic allocation of scan test resources

Low overhead and timing improved architecture for performing error...

Hybrid test compression architecture using multiple codecs for low...

Low overhead and timing improved architecture for performing error...

On-chip seed generation using boolean functions for LFSR re-seeding...

Enhanced control in scan tests of integrated circuits with partitio...

Patents Applicationslast 30 patents

TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION

TESTING OF INTEGRATED CIRCUITS DURING AT-SPEED MODE OF OPERATION

CIRCUITS AND METHODS FOR DYNAMIC ALLOCATION OF SCAN TEST RESOURCES

LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR...

Scan Compression Architecture with Bypassable Scan Chains for Low T...

HYBRID TEST COMPRESSION ARCHITECTURE USING MULTIPLE CODECS FOR LOW...

LOW OVERHEAD AND TIMING IMPROVED ARCHITECTURE FOR PERFORMING ERROR...

ENHANCED CONTROL IN SCAN TESTS OF INTEGRATED CIRCUITS WITH PARTITIO...

On-Chip Seed Generation Using Boolean Functions for LFSR Re-Seeding...