TREA

STANLEY JOHN

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  • FREMONT, CA, US
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Patents Grantslast 30 patents

Patents Applicationslast 30 patents

  • Information Patent Application

    PHASE-LOCKED LOOP MONITOR CIRCUIT
    • Publication number 20210281268
    • Publication date Sep 9, 2021
    • Taiwan Semiconductor Manufacturing Co., LTD
    • Sandeep Kumar GOEL
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Application

    PHASE-LOCKED LOOP MONITOR CIRCUIT
    • Publication number 20200304133
    • Publication date Sep 24, 2020
    • Taiwan Semiconductor Manufacturing Co., LTD
    • Sandeep Kumar GOEL
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Application

    PHASE-LOCKED LOOP MONITOR CIRCUIT
    • Publication number 20190229737
    • Publication date Jul 25, 2019
    • Taiwan Semiconductor Manufacturing Co., LTD
    • Sandeep Kumar GOEL
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Application

    DYNAMIC FREQUENCY SCALING
    • Publication number 20180364783
    • Publication date Dec 20, 2018
    • Taiwan Semiconductor Manufacturing Co., LTD
    • Kai-Yuan TING
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    DEVICE AND METHOD FOR ROBUSTNESS VERIFICATION
    • Publication number 20180164369
    • Publication date Jun 14, 2018
    • Taiwan Semiconductor Manufacturing Co., Ltd.
    • Sandeep Kumar GOEL
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Application

    PHASE-LOCKED LOOP MONITOR CIRCUIT
    • Publication number 20180152193
    • Publication date May 31, 2018
    • Taiwan Semiconductor Manufacturing Co., LTD
    • Sandeep Kumar GOEL
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Application

    POWER STATE COVERAGE METRIC AND METHOD FOR ESTIMATING THE SAME
    • Publication number 20170098023
    • Publication date Apr 6, 2017
    • Taiwan Semiconductor Manufacturing company Ltd.
    • STANLEY JOHN
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    SYSTEM AND METHOD FOR VALIDATING STACKED DIES BY COMPARING CONNECTIONS
    • Publication number 20150234979
    • Publication date Aug 20, 2015
    • Taiwan Semiconductor Manufacturing Co., LTD
    • Ashok MEHTA
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs
    • Publication number 20150123699
    • Publication date May 7, 2015
    • Taiwan Semiconductor Manufacturing Co., LTD
    • Stanley John
    • G01 - MEASURING TESTING
  • Information Patent Application

    DYNAMIC FREQUENCY SCALING
    • Publication number 20130238309
    • Publication date Sep 12, 2013
    • Taiwan Semiconductor Manufacturing Co., LTD
    • Kai-Yuan TING
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    SYSTEM AND METHOD FOR FUNCTIONAL VERIFICATION OF MULTI-DIE 3D ICs
    • Publication number 20130193980
    • Publication date Aug 1, 2013
    • Taiwan Semiconductor Manufacturing Co. Ltd.
    • Stanley JOHN
    • G01 - MEASURING TESTING
  • Information Patent Application

    FORMAT CONVERSION FROM VALUE CHANGE DUMP (VCD) TO UNIVERSAL VERIFIC...
    • Publication number 20130198706
    • Publication date Aug 1, 2013
    • Taiwan Semiconductor Manufacturing Co., LTD
    • Ashok Mehta
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    STACKED DIE INTERCONNECT VALIDATION
    • Publication number 20130167095
    • Publication date Jun 27, 2013
    • Taiwan Semiconductor Manufacturing Co., LTD
    • Ashok MEHTA
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    Generation and Management of Logic
    • Publication number 20080127163
    • Publication date May 29, 2008
    • VIA Technologies, Inc.
    • David Fong
    • G06 - COMPUTING CALCULATING COUNTING
  • Information Patent Application

    Assertion Tester
    • Publication number 20080098366
    • Publication date Apr 24, 2008
    • VIA TECHNOLOGIES, INC.
    • David Fong
    • G06 - COMPUTING CALCULATING COUNTING