Stanley S. Kulick

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses, methods, and systems for package on package memory ref...
- Patent number 10,083,735
- Issue date Sep 25, 2018
- Intel Corporation
- Xiuting C. Man
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preserving deterministic early valid across a clock domain crossing
- Patent number 10,025,732
- Issue date Jul 17, 2018
- Intel Corporation
- Stanley Steve Kulick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for package on package memory ref...
- Patent number 9,653,144
- Issue date May 16, 2017
- Intel Corporation
- Xiuting C. Man
- G11 - INFORMATION STORAGE
Information Patent Grant
Bridging circuitry between a memory controller and request agents i...
- Patent number 9,442,864
- Issue date Sep 13, 2016
- Intel Corporation
- Uday R. Savagaonkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for cache line state update in sectored cache...
- Patent number 9,336,156
- Issue date May 10, 2016
- Intel Corporation
- Zhongying Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deterministic clock crossing
- Patent number 9,285,826
- Issue date Mar 15, 2016
- Intel Corporation
- Stanley Steve Kulick
- G11 - INFORMATION STORAGE
Information Patent Grant
Sideband initialization
- Patent number 9,274,544
- Issue date Mar 1, 2016
- Intel Corporation
- Stanley Steve Kulick
- G11 - INFORMATION STORAGE
Information Patent Grant
Mechanisms for clock gating
- Patent number 9,143,120
- Issue date Sep 22, 2015
- Intel Corporation
- Randy B. Osborne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scalable schedulers for memory controllers
- Patent number 8,977,811
- Issue date Mar 10, 2015
- Intel Corporation
- Philip Abraham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-package input/output clustered interface having full and half-du...
- Patent number 8,902,956
- Issue date Dec 2, 2014
- Intel Corporation
- Thomas P. Thomas
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Scalable schedulers for memory controllers
- Patent number 8,463,987
- Issue date Jun 11, 2013
- Intel Corporation
- Philip Abraham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for adjacent-symbol error correction and detection
- Patent number 8,327,222
- Issue date Dec 4, 2012
- Intel Corporation
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory link training
- Patent number 7,886,174
- Issue date Feb 8, 2011
- Intel Corporation
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for adjacent-symbol error correction and detection
- Patent number 7,509,560
- Issue date Mar 24, 2009
- Intel Corporation
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Mechanism to guarantee forward progress for incoming coherent input...
- Patent number 7,386,643
- Issue date Jun 10, 2008
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method to enable transparent memory hot plug...
- Patent number 7,376,775
- Issue date May 20, 2008
- Intel Corporation
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of sparing memory devices containing pinned memory
- Patent number 7,103,746
- Issue date Sep 5, 2006
- Intel Corporation
- Stanley S. Kulick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory read/write reordering
- Patent number 7,047,374
- Issue date May 16, 2006
- Intel Corporation
- Suneeta Sah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism to guarantee forward progress for incoming coherent input...
- Patent number 6,832,268
- Issue date Dec 14, 2004
- Intel Corporation
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interrupt method, system and medium
- Patent number 6,813,665
- Issue date Nov 2, 2004
- Intel Corporation
- Linda J. Rankin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PRESERVING DETERMINISTIC EARLY VALID ACROSS A CLOCK DOMAIN CROSSING
- Publication number 20180095910
- Publication date Apr 5, 2018
- Intel Corporation
- Stanley Steve KULICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES, METHODS, AND SYSTEMS FOR PACKAGE ON PACKAGE MEMORY REF...
- Publication number 20170372771
- Publication date Dec 28, 2017
- Intel Corporation
- XIUTING C. MAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bridging Circuitry Between A Memory Controller And Request Agents I...
- Publication number 20150186295
- Publication date Jul 2, 2015
- Uday R. Savagaonkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CACHE LINE STATE UPDATE IN SECTORED CACHE...
- Publication number 20140281251
- Publication date Sep 18, 2014
- Zhongying Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIDEBAND INITIALIZATION
- Publication number 20140040652
- Publication date Feb 6, 2014
- Stanley Steve Kulick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISMS FOR CLOCK GATING
- Publication number 20140009195
- Publication date Jan 9, 2014
- Randy B. Osborne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DU...
- Publication number 20130322556
- Publication date Dec 5, 2013
- Thomas P. Thomas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINISTIC CLOCK CROSSING
- Publication number 20130326205
- Publication date Dec 5, 2013
- Stanley Steve Kulick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SCHEDULERS FOR MEMORY CONTROLLERS
- Publication number 20130275664
- Publication date Oct 17, 2013
- Philip Abraham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SCHEDULERS FOR MEMORY CONTROLLERS
- Publication number 20100077140
- Publication date Mar 25, 2010
- Philip Abraham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for Adjacent-Symbol Error Correction and Detection
- Publication number 20090125786
- Publication date May 14, 2009
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY LINK TRAINING
- Publication number 20090006776
- Publication date Jan 1, 2009
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for adjacent-symbol error correction and detection
- Publication number 20050154943
- Publication date Jul 14, 2005
- James W. Alexander
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and method to enable transparent memory hot plug/remove
- Publication number 20050149314
- Publication date Jul 7, 2005
- Lily Pao Looi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism to guarantee forward progress for incoming coherent input...
- Publication number 20050060502
- Publication date Mar 17, 2005
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism to guarantee forward progress for incoming coherent input...
- Publication number 20040122995
- Publication date Jun 24, 2004
- Intel Corporation
- Sin S. Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory read/write reordering
- Publication number 20030177320
- Publication date Sep 18, 2003
- Suneeta Sah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interrupt method, system and medium
- Publication number 20030061423
- Publication date Mar 27, 2003
- Linda J. Rankin
- G06 - COMPUTING CALCULATING COUNTING

Stanley S. Kulick

Person

Patents Grantslast 30 patents

Apparatuses, methods, and systems for package on package memory ref...

Preserving deterministic early valid across a clock domain crossing

Apparatuses, methods, and systems for package on package memory ref...

Bridging circuitry between a memory controller and request agents i...

Method and apparatus for cache line state update in sectored cache...

Deterministic clock crossing

Sideband initialization

Mechanisms for clock gating

Scalable schedulers for memory controllers

On-package input/output clustered interface having full and half-du...

Scalable schedulers for memory controllers

Mechanism for adjacent-symbol error correction and detection

Memory link training

Mechanism for adjacent-symbol error correction and detection

Mechanism to guarantee forward progress for incoming coherent input...

Apparatus, system, and method to enable transparent memory hot plug...

Method of sparing memory devices containing pinned memory

Memory read/write reordering

Mechanism to guarantee forward progress for incoming coherent input...

Interrupt method, system and medium

Patents Applicationslast 30 patents

PRESERVING DETERMINISTIC EARLY VALID ACROSS A CLOCK DOMAIN CROSSING

APPARATUSES, METHODS, AND SYSTEMS FOR PACKAGE ON PACKAGE MEMORY REF...

Bridging Circuitry Between A Memory Controller And Request Agents I...

METHOD AND APPARATUS FOR CACHE LINE STATE UPDATE IN SECTORED CACHE...

SIDEBAND INITIALIZATION

MECHANISMS FOR CLOCK GATING

ON-PACKAGE INPUT/OUTPUT CLUSTERED INTERFACE HAVING FULL AND HALF-DU...

DETERMINISTIC CLOCK CROSSING

SCALABLE SCHEDULERS FOR MEMORY CONTROLLERS

SCALABLE SCHEDULERS FOR MEMORY CONTROLLERS

Mechanism for Adjacent-Symbol Error Correction and Detection

MEMORY LINK TRAINING

Mechanism for adjacent-symbol error correction and detection

Apparatus and method to enable transparent memory hot plug/remove

Mechanism to guarantee forward progress for incoming coherent input...

Mechanism to guarantee forward progress for incoming coherent input...

Memory read/write reordering

Interrupt method, system and medium