Stefan G. Block

Person

Muenchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Edge cell signal line antenna diodes
- Patent number 11,450,753
- Issue date Sep 20, 2022
- GLOBALFOUNDRIES U.S. INC.
- Stefan Block
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor cell for integrated circuits and method to form same
- Patent number 11,329,129
- Issue date May 10, 2022
- GLOBALFOUNDRIES U.S. INC.
- Stefan G. Block
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simplified bias scheme for digital designs
- Patent number 10,505,545
- Issue date Dec 10, 2019
- GLOBALFOUNDRIES Inc.
- Stefan Block
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Placing and routing method for implementing back bias in FDSOI
- Patent number 10,114,919
- Issue date Oct 30, 2018
- GLOBALFOUNDRIES Inc.
- Herbert Johannes Preuthen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing antenna effects in SOI devices
- Patent number 9,773,811
- Issue date Sep 26, 2017
- GLOBALFOUNDRIES Inc.
- Ingolf Lorenz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Clock tree insertion delay independent interface
- Patent number 8,564,337
- Issue date Oct 22, 2013
- LSI Corporation
- Stefan Block
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Generating integrated circuit floorplan layouts
- Patent number 8,219,959
- Issue date Jul 10, 2012
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test pin gating for dynamic optimization
- Patent number 8,078,926
- Issue date Dec 13, 2011
- LSI Corporation
- Stefan G. Block
- G01 - MEASURING TESTING
Information Patent Grant
Adjustable hold flip flop and method for adjusting hold requirements
- Patent number 7,944,237
- Issue date May 17, 2011
- LSI Corporation
- Stephan Habel
- G01 - MEASURING TESTING
Information Patent Grant
Adjustable hold flip flop and method for adjusting hold requirements
- Patent number 7,880,498
- Issue date Feb 1, 2011
- LSI Corporation
- Stephan Habel
- G01 - MEASURING TESTING
Information Patent Grant
N cell height decoupling circuit
- Patent number 7,829,973
- Issue date Nov 9, 2010
- LSI Corporation
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power saving flip-flop
- Patent number 7,650,548
- Issue date Jan 19, 2010
- LSI Corporation
- Stefan G. Block
- G01 - MEASURING TESTING
Information Patent Grant
Config logic power saving method
- Patent number 7,616,517
- Issue date Nov 10, 2009
- LSI Corporation
- Stephan Habel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for adjusting on-chip delay with power supply...
- Patent number 7,514,974
- Issue date Apr 7, 2009
- LSI Corporation
- Stefan G. Block
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital multi-phase clock generator
- Patent number 7,088,158
- Issue date Aug 8, 2006
- LSI Logic Corporation
- Stefan G. Block
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logic built-in self test (BIST)
- Patent number 6,904,554
- Issue date Jun 7, 2005
- LSI Logic Corporation
- Stefan G. Block
- G01 - MEASURING TESTING
Information Patent Grant
Digitally-programmable delay line for multi-phase clock generator
- Patent number 6,756,832
- Issue date Jun 29, 2004
- LSI Logic Corporation
- David R. Reuveni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Matching calibration for digital-to-analog converters
- Patent number 6,667,703
- Issue date Dec 23, 2003
- LSI Logic Corporation
- David R. Reuveni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Matching calibration for dual analog-to-digital converters
- Patent number 6,567,022
- Issue date May 20, 2003
- LSI Corporation
- David R. Reuveni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of providing clock signals to load circuits in an ASIC device
- Patent number 6,313,683
- Issue date Nov 6, 2001
- LSI Logic Corporation
- Stefan Block
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TRANSISTOR CELL FOR INTEGRATED CIRCUITS AND METHOD TO FORM SAME
- Publication number 20210159313
- Publication date May 27, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Stefan G. Block
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EDGE CELL SIGNAL LINE ANTENNA DIODES
- Publication number 20200357897
- Publication date Nov 12, 2020
- GLOBALFOUNDRIES INC.
- Stefan Block
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCING ANTENNA EFFECTS IN SOI DEVICES
- Publication number 20170243894
- Publication date Aug 24, 2017
- GLOBALFOUNDRIES INC.
- Ingolf Lorenz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLACING AND ROUTING METHOD FOR IMPLEMENTING BACK BIAS IN FDSOI
- Publication number 20170235865
- Publication date Aug 17, 2017
- GLOBALFOUNDRIES INC.
- Herbert Johannes Preuthen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL, MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELLS AN...
- Publication number 20160284392
- Publication date Sep 29, 2016
- GLOBALFOUNDRIES INC.
- Stefan Block
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-READ PORT MEMORY
- Publication number 20140281284
- Publication date Sep 18, 2014
- Stefan G. Block
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK TREE INSERTION DELAY INDEPENDENT INTERFACE
- Publication number 20120200322
- Publication date Aug 9, 2012
- LSI Corporation
- Stefan Block
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay-Cell Footprint-Compatible Buffers
- Publication number 20110320997
- Publication date Dec 29, 2011
- LSI Corporation
- Farid Labib
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS
- Publication number 20110084726
- Publication date Apr 14, 2011
- LSI Corporation
- Stephan Habel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Write Through Speed Up for Memory Circuit
- Publication number 20110063926
- Publication date Mar 17, 2011
- LSI Corporation
- Stefan G. Block
- G11 - INFORMATION STORAGE
Information Patent Application
Test Pin Gating for Dynamic Optimization
- Publication number 20110066905
- Publication date Mar 17, 2011
- LSI Corporation
- Stefan G. Block
- G01 - MEASURING TESTING
Information Patent Application
GENERATING INTEGRATED CIRCUIT FLOORPLAN LAYOUTS
- Publication number 20110023000
- Publication date Jan 27, 2011
- LSI Corporation
- Juergen Dirks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS
- Publication number 20090134912
- Publication date May 28, 2009
- LSI Corporation
- Stephan Habel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
N CELL HEIGHT DECOUPLING CIRCUIT
- Publication number 20090051006
- Publication date Feb 26, 2009
- LSI Corporation
- Richard T. Schultz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR ADJUSTING ON-CHIP DELAY WITH POWER SUPPLY...
- Publication number 20080258700
- Publication date Oct 23, 2008
- LSI Logic Corporation
- Stefan G. Block
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER SAVING FLIP-FLOP
- Publication number 20080250283
- Publication date Oct 9, 2008
- LSI Logic Corporation
- Stefan G. Block
- G01 - MEASURING TESTING
Information Patent Application
Digitally-programmable delay line for multi-phase clock generator
- Publication number 20040075481
- Publication date Apr 22, 2004
- David R. Reuveni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Logic built-in self-test (BIST)
- Publication number 20040003330
- Publication date Jan 1, 2004
- LSI Logic Corporation
- Stefan G. Block
- G01 - MEASURING TESTING
Information Patent Application
Digital multi-phase clock generator
- Publication number 20030215039
- Publication date Nov 20, 2003
- Stefan G. Block
- H03 - BASIC ELECTRONIC CIRCUITRY

Stefan G. Block

Person

Patents Grantslast 30 patents

Edge cell signal line antenna diodes

Transistor cell for integrated circuits and method to form same

Simplified bias scheme for digital designs

Placing and routing method for implementing back bias in FDSOI

Reducing antenna effects in SOI devices

Clock tree insertion delay independent interface

Generating integrated circuit floorplan layouts

Test pin gating for dynamic optimization

Adjustable hold flip flop and method for adjusting hold requirements

Adjustable hold flip flop and method for adjusting hold requirements

N cell height decoupling circuit

Power saving flip-flop

Config logic power saving method

Method and apparatus for adjusting on-chip delay with power supply...

Digital multi-phase clock generator

Logic built-in self test (BIST)

Digitally-programmable delay line for multi-phase clock generator

Matching calibration for digital-to-analog converters

Matching calibration for dual analog-to-digital converters

Method of providing clock signals to load circuits in an ASIC device

Patents Applicationslast 30 patents

TRANSISTOR CELL FOR INTEGRATED CIRCUITS AND METHOD TO FORM SAME

EDGE CELL SIGNAL LINE ANTENNA DIODES

REDUCING ANTENNA EFFECTS IN SOI DEVICES

PLACING AND ROUTING METHOD FOR IMPLEMENTING BACK BIAS IN FDSOI

MEMORY CELL, MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY CELLS AN...

MULTI-READ PORT MEMORY

CLOCK TREE INSERTION DELAY INDEPENDENT INTERFACE

Delay-Cell Footprint-Compatible Buffers

ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS

Write Through Speed Up for Memory Circuit

Test Pin Gating for Dynamic Optimization

GENERATING INTEGRATED CIRCUIT FLOORPLAN LAYOUTS

ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS

N CELL HEIGHT DECOUPLING CIRCUIT

METHOD AND APPARATUS FOR ADJUSTING ON-CHIP DELAY WITH POWER SUPPLY...

POWER SAVING FLIP-FLOP

Digitally-programmable delay line for multi-phase clock generator

Logic built-in self-test (BIST)

Digital multi-phase clock generator