Stefan Lammers

Person

Munchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for current sense amplifier calibration in MRA...
- Patent number 7,239,537
- Issue date Jul 3, 2007
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic memory configuration
- Patent number 6,816,406
- Issue date Nov 9, 2004
- Infineon Technologies AG
- Heinz Hönigschmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration and method for the low-loss writing of an MRAM
- Patent number 6,639,829
- Issue date Oct 28, 2003
- Infineon Technologies AG
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Grant
Read/write memory with self-test device and associated test method
- Patent number 6,539,506
- Issue date Mar 25, 2003
- Siemens Aktiengesellschaft
- Stefan Lammers
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip ID register configuration
- Patent number 6,496,423
- Issue date Dec 17, 2002
- Infineon Technologies AG
- Stefan Lammers
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM configuration
- Patent number 6,473,335
- Issue date Oct 29, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration for implementing redundancy for a memory chip
- Patent number 6,459,631
- Issue date Oct 1, 2002
- Infineon Technologies AG
- Helmut Fischer
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS voltage divider
- Patent number 6,429,731
- Issue date Aug 6, 2002
- Infineon Technologies AG
- Thomas Böhm
- G05 - CONTROLLING REGULATING
Information Patent Grant
Integrated semiconductor memory with redundant units for memory cells
- Patent number 6,353,562
- Issue date Mar 5, 2002
- Infineon Technologies AG
- Thomas Böhm
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR CURRENT SENSE AMPLIFIER CALIBRATION IN MRA...
- Publication number 20060152970
- Publication date Jul 13, 2006
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
Magnetic memory configuration
- Publication number 20040100836
- Publication date May 27, 2004
- Heinz Honigschmid
- G11 - INFORMATION STORAGE
Information Patent Application
Configuration and method for the low-loss writing of an MRAM
- Publication number 20020021543
- Publication date Feb 21, 2002
- Dietmar Gogl
- G11 - INFORMATION STORAGE
Information Patent Application
Chip ID register configuration
- Publication number 20020021590
- Publication date Feb 21, 2002
- Stefan Lammers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Configuration for implementing redundancy for a memory chip
- Publication number 20020012281
- Publication date Jan 31, 2002
- Helmut Fischer
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM configuration
- Publication number 20020003720
- Publication date Jan 10, 2002
- Thomas Bohm
- G11 - INFORMATION STORAGE
Information Patent Application
CMOS voltage divider
- Publication number 20010030573
- Publication date Oct 18, 2001
- Thomas Böhm
- G05 - CONTROLLING REGULATING
Information Patent Application
Integrated semiconductor memory with redundant units for memory cells
- Publication number 20010021134
- Publication date Sep 13, 2001
- Thomas Bohm
- G11 - INFORMATION STORAGE

Stefan Lammers

Person

Patents Grantslast 30 patents

Method and apparatus for current sense amplifier calibration in MRA...

Magnetic memory configuration

Configuration and method for the low-loss writing of an MRAM

Read/write memory with self-test device and associated test method

Chip ID register configuration

MRAM configuration

Configuration for implementing redundancy for a memory chip

CMOS voltage divider

Integrated semiconductor memory with redundant units for memory cells

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR CURRENT SENSE AMPLIFIER CALIBRATION IN MRA...

Magnetic memory configuration

Configuration and method for the low-loss writing of an MRAM

Chip ID register configuration

Configuration for implementing redundancy for a memory chip

MRAM configuration

CMOS voltage divider

Integrated semiconductor memory with redundant units for memory cells