Stephan Hoerold

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Sunnyvale, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Density-based layer filler for integrated circuit design
- Patent number 7,565,638
- Issue date Jul 21, 2009
- Sun Microsystems, Inc.
- Stephan Hoerold
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fullchip functional equivalency and physical verification
- Patent number 7,404,161
- Issue date Jul 22, 2008
- Sun Microsystems, Inc.
- Arjun Dutt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit binning and layout design system
- Patent number 7,340,710
- Issue date Mar 4, 2008
- Sun Microsystems, Inc.
- Stephan Hoerold
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock skew verification methodology for grid-based design
- Patent number 6,941,532
- Issue date Sep 6, 2005
- Sun Microsystems, Inc.
- Manjunath D. Haritsa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for topology based noise estimation of submicron...
- Patent number 6,665,845
- Issue date Dec 16, 2003
- Sun Microsystems, Inc.
- Kathirqamar Aingaran
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Density-Based Layer Filler for Integrated Circuit Design
- Publication number 20080120586
- Publication date May 22, 2008
- Stephan Hoerold
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fullchip functional equivalency and physical verification
- Publication number 20060282810
- Publication date Dec 14, 2006
- Arjun Dutt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock skew verification methodology for grid-based design
- Publication number 20030074642
- Publication date Apr 17, 2003
- Sun Microsystems, Inc.
- Manjunath D. Haritsa
- G06 - COMPUTING CALCULATING COUNTING