Stephan Kudelka

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Process to suppress lithography at a wafer edge
- Patent number 6,927,172
- Issue date Aug 9, 2005
- International Business Machines Corporation
- Wolfgang Bergner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structures and manufacturing methods
- Patent number 6,740,555
- Issue date May 25, 2004
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process flow for two-step collar in DRAM preparation
- Patent number 6,670,235
- Issue date Dec 30, 2003
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for surface roughness enhancement in semiconductor capacitor...
- Patent number 6,613,642
- Issue date Sep 2, 2003
- International Business Machines Corporation
- Stephen Rahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structures and manufacturing methods
- Patent number 6,605,860
- Issue date Aug 12, 2003
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single sided buried strap
- Patent number 6,573,137
- Issue date Jun 3, 2003
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch selectivity inversion for etching along crystallographic direc...
- Patent number 6,566,273
- Issue date May 20, 2003
- Infineon Technologies AG
- Stephan Kudelka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process flow for capacitance enhancement in a DRAM trench
- Patent number 6,555,430
- Issue date Apr 29, 2003
- International Business Machines Corporation
- Michael P. Chudzik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical gate top engineering for improved GC and CB process windows
- Patent number 6,518,616
- Issue date Feb 11, 2003
- International Business Machines Corporation
- Thomas W. Dyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Negative ion implant mask formation for self-aligned, sublithograph...
- Patent number 6,498,061
- Issue date Dec 24, 2002
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit trench device with a dielectric collar stack, an...
- Patent number 6,486,024
- Issue date Nov 26, 2002
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process flow for sacrificial collar with poly mask
- Patent number 6,458,647
- Issue date Oct 1, 2002
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for hybrid DRAM cell utilizing confined strap isolation
- Patent number 6,440,872
- Issue date Aug 27, 2002
- International Business Machines Corporation
- Jack A. Mandelman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for improved isolation in trench storage cells
- Patent number 6,437,401
- Issue date Aug 20, 2002
- Infineon Technologies AG
- Jack A. Mandelman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a vertically oriented device in an integrated cir...
- Patent number 6,426,253
- Issue date Jul 30, 2002
- Infineon Technologies A G
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried strap formation without TTO deposition
- Patent number 6,406,970
- Issue date Jun 18, 2002
- Infineon Technologies North America Corp.
- Stephan Kudelka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low temperature self-aligned collar formation
- Patent number 6,352,893
- Issue date Mar 5, 2002
- Infineon Technologies AG
- Alexander Michaelis
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Integrated circuit vertical trench device and method of forming the...
- Patent number 6,335,247
- Issue date Jan 1, 2002
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low temperature sacrificial oxide formation
- Patent number 6,309,983
- Issue date Oct 30, 2001
- Infineon Technologies AG
- Alexander Michaeli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Temperature controlled gassification of deionized water for megason...
- Patent number 6,295,998
- Issue date Oct 2, 2001
- Infineon Technologies North America Corp.
- Stephan Kudelka
- B08 - CLEANING
Information Patent Grant
Method of reducing RIE lag for deep trench silicon etching
- Patent number 6,284,666
- Issue date Sep 4, 2001
- International Business Machines Corporation
- Munir D. Naeem
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual gate oxide process for uniform oxide thickness
- Patent number 6,261,972
- Issue date Jul 17, 2001
- Infineon Technologies AG
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Temperature controlled degassification of deionized water for megas...
- Patent number 6,167,891
- Issue date Jan 2, 2001
- Infineon Technologies North America Corp.
- Stephan Kudelka
- B08 - CLEANING
Information Patent Grant
Method of manufacturing semiconductor structures including a pair o...
- Patent number 6,096,664
- Issue date Aug 1, 2000
- Siemens Aktiengesellschaft
- Thomas S. Rupp
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried strap poly etch back (BSPE) process
- Patent number 6,066,527
- Issue date May 23, 2000
- Infineon Technologies North America Corp.
- Stephan Kudelka
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor structures and manufacturing methods
- Publication number 20040209474
- Publication date Oct 21, 2004
- Helmut Horst Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process to suppress lithography at a wafer edge
- Publication number 20040166677
- Publication date Aug 26, 2004
- International Business Machines Corporation
- Wolfgang Bergner
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method of preparing buried LOCOS collar in trench DRAMS
- Publication number 20030020112
- Publication date Jan 30, 2003
- Helmut Tews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Etch selectivity inversion for etching along crystallographic direc...
- Publication number 20030003759
- Publication date Jan 2, 2003
- Infineon Technologies North America Corp.
- Stephan Kudelka
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vertical gate top engineering for improved GC and CB process windows
- Publication number 20020155654
- Publication date Oct 24, 2002
- International Business Machines Corporation
- Thomas W. Dyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Negative Ion implant mask formation for self-aligned, sublithograph...
- Publication number 20020068399
- Publication date Jun 6, 2002
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR EXPANDING TRENCHES BY AN ANISOTROPIC WET ETCH
- Publication number 20010016398
- Publication date Aug 23, 2001
- STEPHAN KUDELKA
- H01 - BASIC ELECTRIC ELEMENTS

Stephan Kudelka

Person

Patents Grantslast 30 patents

Process to suppress lithography at a wafer edge

Semiconductor structures and manufacturing methods

Process flow for two-step collar in DRAM preparation

Method for surface roughness enhancement in semiconductor capacitor...

Semiconductor structures and manufacturing methods

Single sided buried strap

Etch selectivity inversion for etching along crystallographic direc...

Process flow for capacitance enhancement in a DRAM trench

Vertical gate top engineering for improved GC and CB process windows

Negative ion implant mask formation for self-aligned, sublithograph...

Integrated circuit trench device with a dielectric collar stack, an...

Process flow for sacrificial collar with poly mask

Method for hybrid DRAM cell utilizing confined strap isolation

Structure and method for improved isolation in trench storage cells

Method of forming a vertically oriented device in an integrated cir...

Buried strap formation without TTO deposition

Low temperature self-aligned collar formation

Integrated circuit vertical trench device and method of forming the...

Low temperature sacrificial oxide formation

Temperature controlled gassification of deionized water for megason...

Method of reducing RIE lag for deep trench silicon etching

Dual gate oxide process for uniform oxide thickness

Temperature controlled degassification of deionized water for megas...

Method of manufacturing semiconductor structures including a pair o...

Buried strap poly etch back (BSPE) process

Patents Applicationslast 30 patents

Semiconductor structures and manufacturing methods

Process to suppress lithography at a wafer edge

Method of preparing buried LOCOS collar in trench DRAMS

Etch selectivity inversion for etching along crystallographic direc...

Vertical gate top engineering for improved GC and CB process windows

Negative Ion implant mask formation for self-aligned, sublithograph...

METHOD FOR EXPANDING TRENCHES BY AN ANISOTROPIC WET ETCH