Stephan Niel

Person

Greasque, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Method for manufacturing an electronic device
- Patent number 11,817,484
- Issue date Nov 14, 2023
- STMicroelectronics (Crolles 2) SAS
- Franck Julien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Co-integrated vertically structured capacitive element and fabricat...
- Patent number 11,626,365
- Issue date Apr 11, 2023
- STMicroelectronics (Rousset) SAS
- Abderrezak Marzaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing an electronic device
- Patent number 11,522,057
- Issue date Dec 6, 2022
- STMicroelectronics (Crolles 2) SAS
- Franck Julien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device of physically unclonable function with transistors, and manu...
- Patent number 11,405,223
- Issue date Aug 2, 2022
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with vertically structured capacitive element, a...
- Patent number 11,139,303
- Issue date Oct 5, 2021
- STMicroelectronics (Rousset) SAS
- Abderrezak Marzaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with vertically structured capacitive element, a...
- Patent number 11,081,488
- Issue date Aug 3, 2021
- STMicroelectronics (Rousset) SAS
- Abderrezak Marzaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Co-integrated vertically structured capacitive element and fabricat...
- Patent number 11,004,785
- Issue date May 11, 2021
- STMicroelectronics (Rousset) SAS
- Abderrezak Marzaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method of forming a semiconductor device
- Patent number 10,971,633
- Issue date Apr 6, 2021
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated filler capacitor cell device and corresponding manufactu...
- Patent number 10,943,862
- Issue date Mar 9, 2021
- STMicroelectronics (Rousset) SAS
- Abderrezak Marzaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with vertically structured capacitive element, a...
- Patent number 10,818,669
- Issue date Oct 27, 2020
- STMicroelectronics (Rousset) SAS
- Abderrezak Marzaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for programming a split-gate memory cell and corresponding m...
- Patent number 10,796,763
- Issue date Oct 6, 2020
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Grant
Compact non-volatile memory device of the type with charge trapping...
- Patent number 10,790,293
- Issue date Sep 29, 2020
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with improved resistive region
- Patent number 10,770,357
- Issue date Sep 8, 2020
- STMicroelectronics (Crolles 2) SAS
- Benoît Froment
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell comprising non-self-aligned horizontal and vertical con...
- Patent number 10,686,046
- Issue date Jun 16, 2020
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for fabricating an array of diodes, in particular for a non-...
- Patent number 10,541,270
- Issue date Jan 21, 2020
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact non-volatile memory device of the type with charge trapping...
- Patent number 10,438,960
- Issue date Oct 8, 2019
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell comprising non-self-aligned horizontal and vertical con...
- Patent number 10,403,730
- Issue date Sep 3, 2019
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit with improved resistive region
- Patent number 10,354,926
- Issue date Jul 16, 2019
- STMicroelectronics (Crolles 2) SAS
- Benoît Froment
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device comprising multiple gate structures and method of simultaneo...
- Patent number 10,332,808
- Issue date Jun 25, 2019
- STMicroelectronics (Rousset) SAS
- Franck Julien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical memory cell with non-self-aligned floating drain-source im...
- Patent number 10,192,999
- Issue date Jan 29, 2019
- STMicroelectronics (Rousset) SAS
- Marc Mantelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for forming a PN junction and associated semiconductor device
- Patent number 10,147,733
- Issue date Dec 4, 2018
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for fabricating an array of diodes, in particular for a non-...
- Patent number 10,002,906
- Issue date Jun 19, 2018
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell comprising non-self-aligned horizontal and vertical con...
- Patent number 9,941,369
- Issue date Apr 10, 2018
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Grant
Twin memory cell interconnection structure
- Patent number 9,941,012
- Issue date Apr 10, 2018
- STMICROELECTONICS (ROUSSET) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Grant
Vertical memory cell with non-self-aligned floating drain-source im...
- Patent number 9,876,122
- Issue date Jan 23, 2018
- STMicroelectronics (Rousset) SAS
- Marc Mantelli
- G11 - INFORMATION STORAGE
Information Patent Grant
Read performance of a non-volatile memory device, in particular a n...
- Patent number 9,825,186
- Issue date Nov 21, 2017
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell having a vertical selection gate formed in an FDSOI sub...
- Patent number 9,691,866
- Issue date Jun 27, 2017
- STMicroelectronics (Rousset) SAS
- Arnaud Regnier
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit protected from short circuits caused by silicide
- Patent number 9,666,484
- Issue date May 30, 2017
- STMicroelectronics (Rousset) SAS
- Arnaud Regnier
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Individually read-accessible twin memory cells
- Patent number 9,653,470
- Issue date May 16, 2017
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Grant
Twin memory cell interconnection structure
- Patent number 9,627,068
- Issue date Apr 18, 2017
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICAT...
- Publication number 20230223332
- Publication date Jul 13, 2023
- STMicroelectronics (Rousset) SAS
- Abderrezak MARZAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING INTEGRATED CIRCUITS FROM A SEMICONDUCTOR S...
- Publication number 20230223358
- Publication date Jul 13, 2023
- STMicroelectronics (Crolles 2) SAS
- Carlos Augusto SUAREZ SEGOVIA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE
- Publication number 20230012522
- Publication date Jan 19, 2023
- STMicroelectronics (Crolles 2) SAS
- Franck JULIEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICAT...
- Publication number 20210225757
- Publication date Jul 22, 2021
- STMicroelectronics (Rousset) SAS
- Abderrezak MARZAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE
- Publication number 20210159318
- Publication date May 27, 2021
- STMicroelectronics (Rousset) SAS
- Franck JULIEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and Method of Forming a Semiconductor Device
- Publication number 20210066510
- Publication date Mar 4, 2021
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICAT...
- Publication number 20210057329
- Publication date Feb 25, 2021
- STMicroelectronics (Rousset) SAS
- Abderrezak MARZAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH VERTICALLY STRUCTURED CAPACITIVE ELEMENT, A...
- Publication number 20210005612
- Publication date Jan 7, 2021
- STMicroelectronics (Rousset) SAS
- Abderrezak MARZAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH VERTICALLY STRUCTURED CAPACITIVE ELEMENT, A...
- Publication number 20210005613
- Publication date Jan 7, 2021
- STMicroelectronics (Rousset) SAS
- Abderrezak MARZAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE OF PHYSICALLY UNCLONABLE FUNCTION WITH TRANSISTORS, AND MANU...
- Publication number 20200274722
- Publication date Aug 27, 2020
- STMicroelectronics (Crolles 2) SAS
- Francesco La Rosa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING...
- Publication number 20190371805
- Publication date Dec 5, 2019
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL COMPRISING NON-SELF-ALIGNED HORIZONTAL AND VERTICAL CON...
- Publication number 20190341462
- Publication date Nov 7, 2019
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION
- Publication number 20190287862
- Publication date Sep 19, 2019
- STMicroelectronics (Crolles 2) SAS
- Benoît Froment
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PROGRAMMING A SPLIT-GATE MEMORY CELL AND CORRESPONDING M...
- Publication number 20190237141
- Publication date Aug 1, 2019
- STMicroelectronics (Rousset) SAS
- Francesco LA ROSA
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED FILLER CAPACITOR CELL DEVICE AND CORRESPONDING MANUFACTU...
- Publication number 20190214341
- Publication date Jul 11, 2019
- STMicroelectronics (Rousset) SAS
- Abderrezak MARZAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH VERTICALLY STRUCTURED CAPACITIVE ELEMENT, A...
- Publication number 20190067291
- Publication date Feb 28, 2019
- STMicroelectronics (Rousset) SAS
- Abderrezak MARZAKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a PN Junction and Associated Semiconductor Device
- Publication number 20190067309
- Publication date Feb 28, 2019
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR FABRICATING AN ARRAY OF DIODES, IN PARTICULAR FOR A NON-...
- Publication number 20180294313
- Publication date Oct 11, 2018
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF SIMULTANEOUSLY MANUFACTURING DIFFERENT TRANSISTORS
- Publication number 20180269115
- Publication date Sep 20, 2018
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Franck Julien
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION
- Publication number 20180247874
- Publication date Aug 30, 2018
- STMicroelectronics (Crolles 2) SAS
- Benoît Froment
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL COMPRISING NON-SELF-ALIGNED HORIZONTAL AND VERTICAL CON...
- Publication number 20180197963
- Publication date Jul 12, 2018
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING...
- Publication number 20180151584
- Publication date May 31, 2018
- STMicrielectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL MEMORY CELL WITH NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IM...
- Publication number 20180145183
- Publication date May 24, 2018
- STMicroelectronics (Rousset) SAS
- Marc MANTELLI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING AN ARRAY OF DIODES, IN PARTICULAR FOR A NON-...
- Publication number 20170352703
- Publication date Dec 7, 2017
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Forming a PN Junction and Associated Semiconductor Device
- Publication number 20170345836
- Publication date Nov 30, 2017
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Application
READ PERFORMANCE OF A NON-VOLATILE MEMORY DEVICE, IN PARTICULAR A N...
- Publication number 20170278577
- Publication date Sep 28, 2017
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Application
TWIN MEMORY CELL INTERCONNECTION STRUCTURE
- Publication number 20170178733
- Publication date Jun 22, 2017
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Application
VERTICAL MEMORY CELL WITH NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IM...
- Publication number 20170084749
- Publication date Mar 23, 2017
- STMicroelectronics (Rousset) SAS
- Marc MANTELLI
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL NON-VOLATILE MEMORY CELL COMPRISING AN ERASE TRANSISTOR
- Publication number 20170011804
- Publication date Jan 12, 2017
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUB...
- Publication number 20160372561
- Publication date Dec 22, 2016
- STMicroelectronics (Rousset) SAS
- Arnaud Regnier
- H01 - BASIC ELECTRIC ELEMENTS

Stephan Niel

Person

Patents Grantslast 30 patents

Method for manufacturing an electronic device

Co-integrated vertically structured capacitive element and fabricat...

Method for manufacturing an electronic device

Device of physically unclonable function with transistors, and manu...

Integrated circuit with vertically structured capacitive element, a...

Integrated circuit with vertically structured capacitive element, a...

Co-integrated vertically structured capacitive element and fabricat...

Structure and method of forming a semiconductor device

Integrated filler capacitor cell device and corresponding manufactu...

Integrated circuit with vertically structured capacitive element, a...

Method for programming a split-gate memory cell and corresponding m...

Compact non-volatile memory device of the type with charge trapping...

Integrated circuit with improved resistive region

Memory cell comprising non-self-aligned horizontal and vertical con...

Method for fabricating an array of diodes, in particular for a non-...

Compact non-volatile memory device of the type with charge trapping...

Memory cell comprising non-self-aligned horizontal and vertical con...

Integrated circuit with improved resistive region

Device comprising multiple gate structures and method of simultaneo...

Vertical memory cell with non-self-aligned floating drain-source im...

Method for forming a PN junction and associated semiconductor device

Method for fabricating an array of diodes, in particular for a non-...

Memory cell comprising non-self-aligned horizontal and vertical con...

Twin memory cell interconnection structure

Vertical memory cell with non-self-aligned floating drain-source im...

Read performance of a non-volatile memory device, in particular a n...

Memory cell having a vertical selection gate formed in an FDSOI sub...

Integrated circuit protected from short circuits caused by silicide

Individually read-accessible twin memory cells

Twin memory cell interconnection structure

Patents Applicationslast 30 patents

CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICAT...

METHOD FOR MANUFACTURING INTEGRATED CIRCUITS FROM A SEMICONDUCTOR S...

METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE

CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICAT...

METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE

Structure and Method of Forming a Semiconductor Device

CO-INTEGRATED VERTICALLY STRUCTURED CAPACITIVE ELEMENT AND FABRICAT...

INTEGRATED CIRCUIT WITH VERTICALLY STRUCTURED CAPACITIVE ELEMENT, A...

INTEGRATED CIRCUIT WITH VERTICALLY STRUCTURED CAPACITIVE ELEMENT, A...

DEVICE OF PHYSICALLY UNCLONABLE FUNCTION WITH TRANSISTORS, AND MANU...

COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING...

MEMORY CELL COMPRISING NON-SELF-ALIGNED HORIZONTAL AND VERTICAL CON...

INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION

METHOD FOR PROGRAMMING A SPLIT-GATE MEMORY CELL AND CORRESPONDING M...

INTEGRATED FILLER CAPACITOR CELL DEVICE AND CORRESPONDING MANUFACTU...

INTEGRATED CIRCUIT WITH VERTICALLY STRUCTURED CAPACITIVE ELEMENT, A...

Method for Forming a PN Junction and Associated Semiconductor Device

METHOD FOR FABRICATING AN ARRAY OF DIODES, IN PARTICULAR FOR A NON-...

METHOD OF SIMULTANEOUSLY MANUFACTURING DIFFERENT TRANSISTORS

INTEGRATED CIRCUIT WITH IMPROVED RESISTIVE REGION

MEMORY CELL COMPRISING NON-SELF-ALIGNED HORIZONTAL AND VERTICAL CON...

COMPACT NON-VOLATILE MEMORY DEVICE OF THE TYPE WITH CHARGE TRAPPING...

VERTICAL MEMORY CELL WITH NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IM...

METHOD FOR FABRICATING AN ARRAY OF DIODES, IN PARTICULAR FOR A NON-...

Method for Forming a PN Junction and Associated Semiconductor Device

READ PERFORMANCE OF A NON-VOLATILE MEMORY DEVICE, IN PARTICULAR A N...

TWIN MEMORY CELL INTERCONNECTION STRUCTURE

VERTICAL MEMORY CELL WITH NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IM...

DUAL NON-VOLATILE MEMORY CELL COMPRISING AN ERASE TRANSISTOR

MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUB...