STEPHEN A. FISCHER

Person

SHINGLE SPRINGS, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for booting a heterogeneous system and presenting a symmetri...
- Patent number 10,503,517
- Issue date Dec 10, 2019
- Intel Corporation
- Eliezer Weissmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protection against return oriented programming attacks
- Patent number 10,049,212
- Issue date Aug 14, 2018
- Intel Corporation
- Stephen A. Fischer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Detection of return oriented programming attacks
- Patent number 9,946,875
- Issue date Apr 17, 2018
- Intel Corporation
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a zero voltage processor sleep state
- Patent number 9,874,925
- Issue date Jan 23, 2018
- Intel Corporation
- Sanjeev Jahagirdar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for a zero voltage processor sleep state
- Patent number 9,870,044
- Issue date Jan 16, 2018
- Intel Corporation
- Sanjeev Jahagirdar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for a zero voltage processor sleep state
- Patent number 9,841,807
- Issue date Dec 12, 2017
- Intel Corporation
- Sanjeev Jahagirdar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for booting a heterogeneous system and presenting a symmetri...
- Patent number 9,727,345
- Issue date Aug 8, 2017
- Intel Corporation
- Eliezer Weissmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 9,612,835
- Issue date Apr 4, 2017
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detection of return oriented programming attacks
- Patent number 9,582,663
- Issue date Feb 28, 2017
- Intel Corporation
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a non-deterministic random bit generator (...
- Patent number 9,544,139
- Issue date Jan 10, 2017
- Intel Corporation
- George W. Cox
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 9,383,998
- Issue date Jul 5, 2016
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 9,342,310
- Issue date May 17, 2016
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detection of return oriented programming attacks
- Patent number 9,251,348
- Issue date Feb 2, 2016
- Intel Corporation
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a zero voltage processor
- Patent number 9,235,258
- Issue date Jan 12, 2016
- Intel Corporation
- Sanjeev Jahagirdar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for a zero voltage processor
- Patent number 9,223,389
- Issue date Dec 29, 2015
- Intel Corporation
- Sanjeev Jahagirdar
- G11 - INFORMATION STORAGE
Information Patent Grant
Detection of return oriented programming attacks
- Patent number 9,223,979
- Issue date Dec 29, 2015
- Intel Corporation
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a zero voltage processor
- Patent number 9,223,390
- Issue date Dec 29, 2015
- Intel Corporation
- Sanjeev Jahagirdar
- G11 - INFORMATION STORAGE
Information Patent Grant
Protection against return oriented programming attacks
- Patent number 9,177,147
- Issue date Nov 3, 2015
- Intel Corporation
- Stephen A. Fischer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Protection against return oriented programming attacks
- Patent number 9,177,148
- Issue date Nov 3, 2015
- Intel Corporation
- Stephen A. Fischer
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for a zero voltage processor sleep state
- Patent number 9,141,180
- Issue date Sep 22, 2015
- Intel Corporation
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 9,098,268
- Issue date Aug 4, 2015
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MFENCE and LFENCE micro-architectural implementation method and system
- Patent number 8,959,314
- Issue date Feb 17, 2015
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for establishing safe processor operating points
- Patent number 8,892,861
- Issue date Nov 18, 2014
- Intel Corporation
- Stephen Anthony Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for establishing safe processor operating points
- Patent number 8,850,178
- Issue date Sep 30, 2014
- Intel Corporation
- Stephen Anthony Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for powered off processor core mode
- Patent number 8,707,062
- Issue date Apr 22, 2014
- Intel Corporation
- Sanjeev Jahagirdar
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital random number generator using partially entropic data
- Patent number 8,489,660
- Issue date Jul 16, 2013
- Intel Corporation
- Howard C. Herbert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Detecting spin loops in a virtual machine environment
- Patent number 8,230,203
- Issue date Jul 24, 2012
- Intel Corporation
- Gilbert Neiger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for accessing memory in parallel computing using...
- Patent number 8,171,261
- Issue date May 1, 2012
- Intel Corporation
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for deadlock free bus protection of resources dur...
- Patent number 8,145,816
- Issue date Mar 27, 2012
- Intel Corporation
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for establishing safe processor operating points
- Patent number 8,131,989
- Issue date Mar 6, 2012
- Intel Corporation
- Stephen Anthony Fischer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STACK PIVOT DETECTION SYSTEMS AND METHODS
- Publication number 20180285559
- Publication date Oct 4, 2018
- Rodrigo Branco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRI...
- Publication number 20180060078
- Publication date Mar 1, 2018
- Intel Corporation
- Eliezer Weissmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method And Apparatus For A Zero Voltage Processor Sleep State
- Publication number 20170269672
- Publication date Sep 21, 2017
- Intel Corporation
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM
- Publication number 20170206088
- Publication date Jul 20, 2017
- lntel Corporation
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detection Of Return Oriented Programming Attacks
- Publication number 20170116414
- Publication date Apr 27, 2017
- Intel Corporation
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method And Apparatus For A Zero Voltage Processor Sleep State
- Publication number 20170017297
- Publication date Jan 19, 2017
- Intel Corporation
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method And Apparatus For A Zero Voltage Processor Sleep State
- Publication number 20160098075
- Publication date Apr 7, 2016
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR A ZERO VOLTAGE PROCESSOR SLEEP STATE
- Publication number 20160091958
- Publication date Mar 31, 2016
- Intel Corporation
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detection Of Return Oriented Programming Attacks
- Publication number 20160085966
- Publication date Mar 24, 2016
- Intel Corporation
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Protection Against Return Oriented Programming Attacks
- Publication number 20160012229
- Publication date Jan 14, 2016
- Intel Corporation
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method And Apparatus For A Zero Voltage Processor Sleep State
- Publication number 20150169043
- Publication date Jun 18, 2015
- Intel Corporation
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method And Apparatus For A Zero Voltage Processor
- Publication number 20150058667
- Publication date Feb 26, 2015
- Intel Corporation
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR A NON-DETERMINISTIC RANDOM BIT GENERATOR (...
- Publication number 20150055778
- Publication date Feb 26, 2015
- George W. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method And Apparatus For A Zero Voltage Processor
- Publication number 20150052377
- Publication date Feb 19, 2015
- Intel Corporation
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method And Apparatus For A Zero Voltage Processor
- Publication number 20150006938
- Publication date Jan 1, 2015
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRI...
- Publication number 20140281457
- Publication date Sep 18, 2014
- Elierzer Weissmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETECTION OF RETURN ORIENTED PROGRAMMING ATTACKS
- Publication number 20140123281
- Publication date May 1, 2014
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detection Of Return Oriented Programming Attacks
- Publication number 20140123286
- Publication date May 1, 2014
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Protection Against Return Oriented Programming Attacks
- Publication number 20140096245
- Publication date Apr 3, 2014
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Protection Against Return Oriented Programming Attacks
- Publication number 20140096247
- Publication date Apr 3, 2014
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE and LFENCE Micro-Architectural Implementation Method and System
- Publication number 20130305018
- Publication date Nov 14, 2013
- SALVADOR PALANCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ESTABLISHING SAFE PROCESSOR OPERATING POINTS
- Publication number 20130212370
- Publication date Aug 15, 2013
- Stephen A. Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM
- Publication number 20130205117
- Publication date Aug 8, 2013
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM
- Publication number 20130073834
- Publication date Mar 21, 2013
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM
- Publication number 20130067200
- Publication date Mar 14, 2013
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ESTABLISHING SAFE PROCESSOR OPERATING POINTS
- Publication number 20130013909
- Publication date Jan 10, 2013
- Stephen Anthony Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR A ZERO VOLTAGE PROCESSOR SLEEP STATE
- Publication number 20130013945
- Publication date Jan 10, 2013
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MFENCE and LFENCE Micro-Architectural Implementation Method and System
- Publication number 20120191951
- Publication date Jul 26, 2012
- Salvador Palanca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ESTABLISHING SAFE PROCESSOR OPERATING POINTS
- Publication number 20120137120
- Publication date May 31, 2012
- Stephen Anthony Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR A ZERO VOLTAGE PROCESSOR SLEEP STATE
- Publication number 20120072750
- Publication date Mar 22, 2012
- Sanjeev Jahagirdar
- G06 - COMPUTING CALCULATING COUNTING

STEPHEN A. FISCHER

Person

Patents Grantslast 30 patents

Method for booting a heterogeneous system and presenting a symmetri...

Protection against return oriented programming attacks

Detection of return oriented programming attacks

Method and apparatus for a zero voltage processor sleep state

Method and apparatus for a zero voltage processor sleep state

Method and apparatus for a zero voltage processor sleep state

Method for booting a heterogeneous system and presenting a symmetri...

MFENCE and LFENCE micro-architectural implementation method and system

Detection of return oriented programming attacks

Method and apparatus for a non-deterministic random bit generator (...

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

Detection of return oriented programming attacks

Method and apparatus for a zero voltage processor

Method and apparatus for a zero voltage processor

Detection of return oriented programming attacks

Method and apparatus for a zero voltage processor

Protection against return oriented programming attacks

Protection against return oriented programming attacks

Method and apparatus for a zero voltage processor sleep state

MFENCE and LFENCE micro-architectural implementation method and system

MFENCE and LFENCE micro-architectural implementation method and system

Method and apparatus for establishing safe processor operating points

Method and apparatus for establishing safe processor operating points

Method and apparatus for powered off processor core mode

Digital random number generator using partially entropic data

Detecting spin loops in a virtual machine environment

Method and system for accessing memory in parallel computing using...

System and method for deadlock free bus protection of resources dur...

Method and apparatus for establishing safe processor operating points

Patents Applicationslast 30 patents

STACK PIVOT DETECTION SYSTEMS AND METHODS

METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRI...

Method And Apparatus For A Zero Voltage Processor Sleep State

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

Detection Of Return Oriented Programming Attacks

Method And Apparatus For A Zero Voltage Processor Sleep State

Method And Apparatus For A Zero Voltage Processor Sleep State

METHOD AND APPARATUS FOR A ZERO VOLTAGE PROCESSOR SLEEP STATE

Detection Of Return Oriented Programming Attacks

Protection Against Return Oriented Programming Attacks

Method And Apparatus For A Zero Voltage Processor Sleep State

Method And Apparatus For A Zero Voltage Processor

METHOD AND APPARATUS FOR A NON-DETERMINISTIC RANDOM BIT GENERATOR (...

Method And Apparatus For A Zero Voltage Processor

Method And Apparatus For A Zero Voltage Processor

METHOD FOR BOOTING A HETEROGENEOUS SYSTEM AND PRESENTING A SYMMETRI...

DETECTION OF RETURN ORIENTED PROGRAMMING ATTACKS

Detection Of Return Oriented Programming Attacks

Protection Against Return Oriented Programming Attacks

Protection Against Return Oriented Programming Attacks

MFENCE and LFENCE Micro-Architectural Implementation Method and System

METHOD AND APPARATUS FOR ESTABLISHING SAFE PROCESSOR OPERATING POINTS

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

MFENCE AND LFENCE MICRO-ARCHITECTURAL IMPLEMENTATION METHOD AND SYSTEM

METHOD AND APPARATUS FOR ESTABLISHING SAFE PROCESSOR OPERATING POINTS

METHOD AND APPARATUS FOR A ZERO VOLTAGE PROCESSOR SLEEP STATE

MFENCE and LFENCE Micro-Architectural Implementation Method and System

METHOD AND APPARATUS FOR ESTABLISHING SAFE PROCESSOR OPERATING POINTS

METHOD AND APPARATUS FOR A ZERO VOLTAGE PROCESSOR SLEEP STATE