Stephen D. Brown

Person

Toronto, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Registering content to a digital locker
- Patent number 10,057,228
- Issue date Aug 21, 2018
- CT ACQUISITION HOLDCO, LLC
- Steve Brown
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for implementing soft constraints in tools use...
- Patent number 9,754,065
- Issue date Sep 5, 2017
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing multiple stage physical synthesis
- Patent number 9,589,090
- Issue date Mar 7, 2017
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing compilation using multiple desi...
- Patent number 9,122,826
- Issue date Sep 1, 2015
- Altera Corporation
- Terry Borer
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for performing multiple stage physical synthesis
- Patent number 8,856,702
- Issue date Oct 7, 2014
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing soft constraints in tools use...
- Patent number 8,589,849
- Issue date Nov 19, 2013
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
M/A for performing incremental compilation using top-down and botto...
- Patent number 8,589,838
- Issue date Nov 19, 2013
- Altera Corporation
- Terry Borer
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for performing multiple stage physical synthesis
- Patent number 8,510,688
- Issue date Aug 13, 2013
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing simultaneous register retiming...
- Patent number 8,296,696
- Issue date Oct 23, 2012
- Altera Corporation
- Gordon Raymond Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing incremental compilation using t...
- Patent number 8,250,505
- Issue date Aug 21, 2012
- Altera Corporation
- Terry Borer
- G01 - MEASURING TESTING
Information Patent Grant
Methods for instruction trace decomposition
- Patent number 8,095,914
- Issue date Jan 10, 2012
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing multiple stage physical synthesis
- Patent number 7,996,797
- Issue date Aug 9, 2011
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for mapping arbitrary logic functions into sync...
- Patent number 7,797,666
- Issue date Sep 14, 2010
- Altera Corporation
- Gordon Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing incremental compilation using t...
- Patent number 7,669,157
- Issue date Feb 23, 2010
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing post-placement routability opti...
- Patent number 7,620,925
- Issue date Nov 17, 2009
- Altera Corporation
- Valavan Manohararajah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for automated sweeping of parameters in computer-aided d...
- Patent number 7,594,208
- Issue date Sep 22, 2009
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing layout-driven optimizations on...
- Patent number 7,594,204
- Issue date Sep 22, 2009
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing post-placement functional decom...
- Patent number 7,509,597
- Issue date Mar 24, 2009
- Altera Corporation
- Valavan Manohararajah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing physical synthesis hill-climbin...
- Patent number 7,500,216
- Issue date Mar 3, 2009
- Altera Corporation
- Ivan Blunno
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing incremental compilation
- Patent number 7,464,362
- Issue date Dec 9, 2008
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for mapping arbitrary logic functions into sync...
- Patent number 7,444,613
- Issue date Oct 28, 2008
- Altera Corporation
- Gordon Chiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting reducible registers
- Patent number 7,412,677
- Issue date Aug 12, 2008
- Altera Corporation
- Valavan Manohararajah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing compound duplication of compone...
- Patent number 7,401,314
- Issue date Jul 15, 2008
- Altera Corporation
- Karl Schabas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for editing circuit design files to be compatible with a...
- Patent number 7,389,489
- Issue date Jun 17, 2008
- Altera Corporation
- Ian Chesal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing retiming on field programmable...
- Patent number 7,360,190
- Issue date Apr 15, 2008
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing incremental placement for layou...
- Patent number 7,318,210
- Issue date Jan 8, 2008
- Altera Corporation
- Deshanand P. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesis aware placement: a novel approach that combines knowledge...
- Patent number 7,254,801
- Issue date Aug 7, 2007
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for designing systems using logic regions
- Patent number 7,197,734
- Issue date Mar 27, 2007
- Altera Corporation
- Deshanand P. Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing soft constraints in tools use...
- Patent number 7,194,720
- Issue date Mar 20, 2007
- Altera Corporation
- Terry P. Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing incremental compilation on fiel...
- Patent number 7,191,426
- Issue date Mar 13, 2007
- Altera Corporation
- Deshanand Singh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Implementing Soft Constraints in Tools Use...
- Publication number 20170337318
- Publication date Nov 23, 2017
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTERING CONTENT TO A DIGITAL LOCKER
- Publication number 20150304296
- Publication date Oct 22, 2015
- CINRAM GROUP, INC.
- Steve Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Implementing Soft Constraints in Tools Use...
- Publication number 20140047405
- Publication date Feb 13, 2014
- Altera Corporation
- Terry Borer
- G06 - COMPUTING CALCULATING COUNTING

Stephen D. Brown

Person

Patents Grantslast 30 patents

Registering content to a digital locker

Method and apparatus for implementing soft constraints in tools use...

Method and apparatus for performing multiple stage physical synthesis

Method and apparatus for performing compilation using multiple desi...

Method and apparatus for performing multiple stage physical synthesis

Method and apparatus for implementing soft constraints in tools use...

M/A for performing incremental compilation using top-down and botto...

Method and apparatus for performing multiple stage physical synthesis

Method and apparatus for performing simultaneous register retiming...

Method and apparatus for performing incremental compilation using t...

Methods for instruction trace decomposition

Method and apparatus for performing multiple stage physical synthesis

Systems and methods for mapping arbitrary logic functions into sync...

Method and apparatus for performing incremental compilation using t...

Method and apparatus for performing post-placement routability opti...

Techniques for automated sweeping of parameters in computer-aided d...

Method and apparatus for performing layout-driven optimizations on...

Method and apparatus for performing post-placement functional decom...

Method and apparatus for performing physical synthesis hill-climbin...

Method and apparatus for performing incremental compilation

Systems and methods for mapping arbitrary logic functions into sync...

Detecting reducible registers

Method and apparatus for performing compound duplication of compone...

Techniques for editing circuit design files to be compatible with a...

Method and apparatus for performing retiming on field programmable...

Method and apparatus for performing incremental placement for layou...

Synthesis aware placement: a novel approach that combines knowledge...

Method and apparatus for designing systems using logic regions

Method and apparatus for implementing soft constraints in tools use...

Method and apparatus for performing incremental compilation on fiel...

Patents Applicationslast 30 patents

Method and Apparatus for Implementing Soft Constraints in Tools Use...

REGISTERING CONTENT TO A DIGITAL LOCKER

Method and Apparatus for Implementing Soft Constraints in Tools Use...