Stephen D. Hanna

Person

Longmont, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated pivot table in a logical-to-physical mapping
- Patent number 12,216,943
- Issue date Feb 4, 2025
- Giuseppe D'Eliseo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential data optimized sub-regions in storage devices
- Patent number 12,135,887
- Issue date Nov 5, 2024
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address verification at a memory system
- Patent number 12,124,738
- Issue date Oct 22, 2024
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Notifying memory system of host events via modulated reset signals
- Patent number 12,056,518
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Qing Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system performance shaping including controlling data tr...
- Patent number 12,014,048
- Issue date Jun 18, 2024
- Micron Technology, Inc.
- Douglas E. Majerus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device reset alert mechanism
- Patent number 11,994,951
- Issue date May 28, 2024
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Creating high density logical to physical mapping
- Patent number 11,940,926
- Issue date Mar 26, 2024
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated pivot table in a logical-to-physical mapping
- Patent number 11,941,300
- Issue date Mar 26, 2024
- Giuseppe D'Eliseo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low cost and low latency logical unit erase
- Patent number 11,815,939
- Issue date Nov 14, 2023
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host-based flash memory maintenance techniques
- Patent number 11,809,311
- Issue date Nov 7, 2023
- Micron Technology, Inc.
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to perform a write operation
- Patent number 11,775,207
- Issue date Oct 3, 2023
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential data optimized sub-regions in storage devices
- Patent number 11,755,214
- Issue date Sep 12, 2023
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory error correction based on layered error detection
- Patent number 11,716,096
- Issue date Aug 1, 2023
- Micron Technology, Inc.
- Stephen D. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Facilitating sequential reads in memory sub-systems
- Patent number 11,704,256
- Issue date Jul 18, 2023
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signaling mechanism for bus inversion
- Patent number 11,687,477
- Issue date Jun 27, 2023
- Micron Technology, Inc.
- Stephen D. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing reduced power memory operations
- Patent number 11,656,673
- Issue date May 23, 2023
- Micron Technology, Inc.
- Qing Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system performance shaping including adding a delay to p...
- Patent number 11,630,579
- Issue date Apr 18, 2023
- Micron Technology, Inc.
- Douglas E. Majerus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inserting temperature information into a codeword
- Patent number 11,625,299
- Issue date Apr 11, 2023
- Micron Technology, Inc.
- Stephen D. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electrical device with test interface
- Patent number 11,568,953
- Issue date Jan 31, 2023
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated pivot table in a logical-to-physical mapping having entr...
- Patent number 11,520,525
- Issue date Dec 6, 2022
- Micron Technology, Inc.
- Giuseppe D'Eliseo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Notifying memory system of host events via modulated reset signals
- Patent number 11,513,835
- Issue date Nov 29, 2022
- Micron Technology, Inc.
- Qing Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low cost and low latency logical unit erase
- Patent number 11,347,659
- Issue date May 31, 2022
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory error correction based on layered error detection
- Patent number 11,329,673
- Issue date May 10, 2022
- Micron Technology, Inc.
- Stephen D. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential data optimized sub-regions in storage devices
- Patent number 11,294,585
- Issue date Apr 5, 2022
- Micron Technology, Inc.
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signaling mechanism for bus inversion
- Patent number 11,294,838
- Issue date Apr 5, 2022
- Micron Technology, Inc.
- Stephen D. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host-based flash memory maintenance techniques
- Patent number 11,226,894
- Issue date Jan 18, 2022
- Micron Technology, Inc.
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Facilitating sequential reads in memory sub-systems
- Patent number 11,200,179
- Issue date Dec 14, 2021
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mapping table compression using a run length encoding algorithm
- Patent number 10,970,228
- Issue date Apr 6, 2021
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage device with test interface
- Patent number 10,930,366
- Issue date Feb 23, 2021
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential data optimized sub-regions in storage devices
- Patent number 10,871,907
- Issue date Dec 22, 2020
- Micron Technology, Inc.
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ADDRESS VERIFICATION AT A MEMORY SYSTEM
- Publication number 20250103245
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
- Publication number 20250021250
- Publication date Jan 16, 2025
- Lodestar Licensing Group, LLC
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE RESET ALERT MECHANISM
- Publication number 20240354195
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CREATING HIGH DENSITY LOGICAL TO PHYSICAL MAPPING
- Publication number 20240289279
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING FOR MEMORY DEVICES USING DEDICATED COMMAND AND ADDRESS CHAN...
- Publication number 20240281350
- Publication date Aug 22, 2024
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST ASSISTED LINK START
- Publication number 20240241793
- Publication date Jul 18, 2024
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED PIVOT TABLE IN A LOGICAL-TO-PHYSICAL MAPPING
- Publication number 20240220162
- Publication date Jul 4, 2024
- Lodestar Licensing Group LLC
- Giuseppe D'Eliseo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PEAK POWER MANAGEMENT EXTENSIONS TO APPLICATION-SPECIFIC INTEGRATED...
- Publication number 20240168536
- Publication date May 23, 2024
- Micron Technology, Inc.
- Liang Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION AND DECOMPRESSION OF TRIM DATA
- Publication number 20240053905
- Publication date Feb 15, 2024
- Micron Technology, Inc.
- Reshmi Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS VERIFICATION AT A MEMORY SYSTEM
- Publication number 20240045617
- Publication date Feb 8, 2024
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW COST AND LOW LATENCY LOGICAL UNIT ERASE
- Publication number 20240045812
- Publication date Feb 8, 2024
- Lodestar Licensing Group, LLC
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER BOOT-UP FOR MEMORY SYSTEMS
- Publication number 20240045596
- Publication date Feb 8, 2024
- Micron Technology, Inc.
- Reshmi Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
- Publication number 20240020033
- Publication date Jan 18, 2024
- Lodestar Licensing Group, LLC
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CREATING HIGH DENSITY LOGICAL TO PHYSICAL MAPPING
- Publication number 20230367718
- Publication date Nov 16, 2023
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC POWER MODES FOR BOOT-UP PROCEDURES
- Publication number 20230305617
- Publication date Sep 28, 2023
- Micron Technology, Inc.
- Luca Porzio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE RESET ALERT MECHANISM
- Publication number 20230267047
- Publication date Aug 24, 2023
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO PERFORM A WRITE OPERATION
- Publication number 20230259304
- Publication date Aug 17, 2023
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SUB-SYSTEM PERFORMANCE SHAPING
- Publication number 20230214120
- Publication date Jul 6, 2023
- Micron Technology, Inc.
- Douglas E. Majerus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED PIVOT TABLE IN A LOGICAL-TO-PHYSICAL MAPPING
- Publication number 20230111015
- Publication date Apr 13, 2023
- Micron Technology, Inc.
- Giuseppe D'Eliseo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOTIFYING MEMORY SYSTEM OF HOST EVENTS VIA MODULATED RESET SIGNALS
- Publication number 20230027877
- Publication date Jan 26, 2023
- Micron Technology, Inc.
- Qing Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED PIVOT TABLE IN A LOGICAL-TO-PHYSICAL MAPPING HAVING ENTR...
- Publication number 20220357884
- Publication date Nov 10, 2022
- Micron Technology, Inc.
- Giuseppe D'Eliseo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ERROR CORRECTION BASED ON LAYERED ERROR DETECTION
- Publication number 20220337271
- Publication date Oct 20, 2022
- Micron Technology, Inc.
- Stephen D. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW COST AND LOW LATENCY LOGICAL UNIT ERASE
- Publication number 20220276970
- Publication date Sep 1, 2022
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
- Publication number 20220214821
- Publication date Jul 7, 2022
- Micron Technology, Inc.
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNALING MECHANISM FOR BUS INVERSION
- Publication number 20220206981
- Publication date Jun 30, 2022
- Micron Technology, Inc.
- Stephen D. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FACILITATING SEQUENTIAL READS IN MEMORY SUB-SYSTEMS
- Publication number 20220058138
- Publication date Feb 24, 2022
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNALING MECHANISM FOR BUS INVERSION
- Publication number 20220035758
- Publication date Feb 3, 2022
- Micron Technology, Inc.
- Stephen D. Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOTIFYING MEMORY SYSTEM OF HOST EVENTS VIA MODULATED RESET SIGNALS
- Publication number 20210373939
- Publication date Dec 2, 2021
- Micron Technology, Inc.
- Qing Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST-BASED FLASH MEMORY MAINTENANCE TECHNIQUES
- Publication number 20210365364
- Publication date Nov 25, 2021
- Micron Technology, Inc.
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FACILITATING SEQUENTIAL READS IN MEMORY SUB-SYSTEMS
- Publication number 20210263864
- Publication date Aug 26, 2021
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING

Stephen D. Hanna

Person

Patents Grantslast 30 patents

Integrated pivot table in a logical-to-physical mapping

Sequential data optimized sub-regions in storage devices

Address verification at a memory system

Notifying memory system of host events via modulated reset signals

Memory sub-system performance shaping including controlling data tr...

Device reset alert mechanism

Creating high density logical to physical mapping

Integrated pivot table in a logical-to-physical mapping

Low cost and low latency logical unit erase

Host-based flash memory maintenance techniques

Techniques to perform a write operation

Sequential data optimized sub-regions in storage devices

Memory error correction based on layered error detection

Facilitating sequential reads in memory sub-systems

Signaling mechanism for bus inversion

Managing reduced power memory operations

Memory sub-system performance shaping including adding a delay to p...

Inserting temperature information into a codeword

Electrical device with test interface

Integrated pivot table in a logical-to-physical mapping having entr...

Notifying memory system of host events via modulated reset signals

Low cost and low latency logical unit erase

Memory error correction based on layered error detection

Sequential data optimized sub-regions in storage devices

Signaling mechanism for bus inversion

Host-based flash memory maintenance techniques

Facilitating sequential reads in memory sub-systems

Mapping table compression using a run length encoding algorithm

Storage device with test interface

Sequential data optimized sub-regions in storage devices

Patents Applicationslast 30 patents

ADDRESS VERIFICATION AT A MEMORY SYSTEM

SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES

DEVICE RESET ALERT MECHANISM

CREATING HIGH DENSITY LOGICAL TO PHYSICAL MAPPING

TESTING FOR MEMORY DEVICES USING DEDICATED COMMAND AND ADDRESS CHAN...

HOST ASSISTED LINK START

INTEGRATED PIVOT TABLE IN A LOGICAL-TO-PHYSICAL MAPPING

PEAK POWER MANAGEMENT EXTENSIONS TO APPLICATION-SPECIFIC INTEGRATED...

COMPRESSION AND DECOMPRESSION OF TRIM DATA

ADDRESS VERIFICATION AT A MEMORY SYSTEM

LOW COST AND LOW LATENCY LOGICAL UNIT ERASE

LOW-POWER BOOT-UP FOR MEMORY SYSTEMS

SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES

CREATING HIGH DENSITY LOGICAL TO PHYSICAL MAPPING

DYNAMIC POWER MODES FOR BOOT-UP PROCEDURES

DEVICE RESET ALERT MECHANISM

TECHNIQUES TO PERFORM A WRITE OPERATION

MEMORY SUB-SYSTEM PERFORMANCE SHAPING

INTEGRATED PIVOT TABLE IN A LOGICAL-TO-PHYSICAL MAPPING

NOTIFYING MEMORY SYSTEM OF HOST EVENTS VIA MODULATED RESET SIGNALS

INTEGRATED PIVOT TABLE IN A LOGICAL-TO-PHYSICAL MAPPING HAVING ENTR...

MEMORY ERROR CORRECTION BASED ON LAYERED ERROR DETECTION

LOW COST AND LOW LATENCY LOGICAL UNIT ERASE

SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES

SIGNALING MECHANISM FOR BUS INVERSION

FACILITATING SEQUENTIAL READS IN MEMORY SUB-SYSTEMS

SIGNALING MECHANISM FOR BUS INVERSION

NOTIFYING MEMORY SYSTEM OF HOST EVENTS VIA MODULATED RESET SIGNALS

HOST-BASED FLASH MEMORY MAINTENANCE TECHNIQUES

FACILITATING SEQUENTIAL READS IN MEMORY SUB-SYSTEMS