Stephen H. Hall

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self-equalized and self-crosstalk-compensated 3D transmission line...
- Patent number 11,955,436
- Issue date Apr 9, 2024
- Intel Corporation
- Khang Choong Yong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pattern-edged metal-plane resonance-suppression
- Patent number 11,729,900
- Issue date Aug 15, 2023
- Intel Corporation
- Stephen Harvey Hall
- G05 - CONTROLLING REGULATING
Information Patent Grant
Stiffener and package substrate for a semiconductor package
- Patent number 11,295,998
- Issue date Apr 5, 2022
- Intel Corporation
- Stephen Christianson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Crystal oscillator interconnect architecture with noise immunity
- Patent number 11,290,059
- Issue date Mar 29, 2022
- Intel Corporation
- Khang Choong Yong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pattern-edged metal-plane resonance-suppression
- Patent number 11,277,903
- Issue date Mar 15, 2022
- Intel Corporation
- Stephen Harvey Hall
- G05 - CONTROLLING REGULATING
Information Patent Grant
Flexible printed circuit EMI enclosure
- Patent number 11,178,768
- Issue date Nov 16, 2021
- Intel Corporation
- Khang Choong Yong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-layer, self-equalizing interconnects in package substrates
- Patent number 10,886,209
- Issue date Jan 5, 2021
- Intel Corporation
- Stephen Harvey Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System to provide tactile feedback during non-contact interaction
- Patent number 10,877,559
- Issue date Dec 29, 2020
- Intel Corporation
- Kevin J. Doran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transmission line design with routing-over-void compensation
- Patent number 10,856,407
- Issue date Dec 1, 2020
- Intel Corporation
- Khang Choong Yong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mutual inductance suppressor for crosstalk immunity enhancement
- Patent number 10,652,999
- Issue date May 12, 2020
- Intel Corporation
- Khang Choong Yong
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Crystal oscillator interconnect architecture with noise immunity
- Patent number 10,516,366
- Issue date Dec 24, 2019
- Intel Corporation
- Khang Choong Yong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Routing-over-void-T-line-compensation
- Patent number 10,484,231
- Issue date Nov 19, 2019
- Intel Corporation
- Khang Choong Yong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Electrical interconnect for a flexible electronic package
- Patent number 10,354,957
- Issue date Jul 16, 2019
- Intel Corporation
- Bok Eng Cheah
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Crystal oscillator interconnect architecture with noise immunity
- Patent number 10,171,033
- Issue date Jan 1, 2019
- Intel Corporation
- Khang Choong Yong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mode selective balanced encoded interconnect
- Patent number 10,078,612
- Issue date Sep 18, 2018
- Intel Corporation
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic-based decoder for crosstalk-harnessed signaling
- Patent number 10,073,807
- Issue date Sep 11, 2018
- Intel Corporation
- Chaitanya Sreerama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Crosstalk aware decoding for a data bus
- Patent number 9,632,961
- Issue date Apr 25, 2017
- Intel Corporation
- Olufemi B. Oluwafemi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electrical interconnect for an electronic package
- Patent number 9,552,995
- Issue date Jan 24, 2017
- Intel Corporation
- Khang Choong Yong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structures for edge-to-edge coupling with flexible circuitry
- Patent number 9,515,402
- Issue date Dec 6, 2016
- Intel Corporation
- Xiang Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Crosstalk aware encoding for a data bus
- Patent number 9,330,039
- Issue date May 3, 2016
- Intel Corporation
- Stephen H. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of forming a high speed interconnect
- Patent number 8,732,942
- Issue date May 27, 2014
- Intel Corporation
- Stephen H. Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Shifted segment layout for differential signal traces to mitigate b...
- Patent number 7,977,581
- Issue date Jul 12, 2011
- Intel Corporation
- Tao Liang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Ultra-high bandwidth interconnect for data transmission
- Patent number 7,800,459
- Issue date Sep 21, 2010
- Intel Corporation
- Stephen H. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Managing system clocks to reduce RFI
- Patent number 7,761,057
- Issue date Jul 20, 2010
- Intel Corporation
- Chaitanya Sreerama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shifted segment layout for differential signal traces to mitigate b...
- Patent number 7,723,618
- Issue date May 25, 2010
- Intel Corporation
- Tao Liang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Modular waveguide inteconnect
- Patent number 7,495,623
- Issue date Feb 24, 2009
- Gary Brist
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flexible waveguide cable with coupling antennas for digital signals
- Patent number 7,474,178
- Issue date Jan 6, 2009
- Intel Corporation
- Ricardo Suarez-Gartner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shifted segment layout for differential signal traces to mitigate b...
- Patent number 7,427,719
- Issue date Sep 23, 2008
- Intel Corporation
- Tao Liang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Flexible waveguide cable with a dielectric core
- Patent number 7,301,424
- Issue date Nov 27, 2007
- Intel Corporation
- Ricardo Suarez-Gartner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus, and system for parallel plate mode radial patter...
- Patent number 7,271,680
- Issue date Sep 18, 2007
- Intel Corporation
- Stephen Hall
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ROTATING CIRCULAR WAVEGUIDE CHANNEL FOR FOLDABLE ELECTRONIC DEVICES
- Publication number 20250004222
- Publication date Jan 2, 2025
- Intel Corporation
- Debabani Choudhury
- G02 - OPTICS
Information Patent Application
ENCODING DIFFERENTIAL SIGNALS FOR POWER AND NOISE REDUCTION
- Publication number 20240329715
- Publication date Oct 3, 2024
- Intel Corporation
- Amit K. Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PATTERN-EDGED METAL-PLANE RESONANCE-SUPPRESSION
- Publication number 20220304143
- Publication date Sep 22, 2022
- Intel Corporation
- Stephen Harvey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
TECHNOLOGIES FOR A LOW-NOISE-GENERATING INDUCTOR
- Publication number 20220223330
- Publication date Jul 14, 2022
- Long Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWISTED DIFFERENTIAL COMPENSATION FOR ROUTING HIGH-SPEED SIGNALS NE...
- Publication number 20210392743
- Publication date Dec 16, 2021
- Intel Corporation
- Long WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-EQUALIZED AND SELF-CROSSTALK-COMPENSATED 3D TRANSMISSION LINE...
- Publication number 20200343194
- Publication date Oct 29, 2020
- Intel Corporation
- Khang Choong YONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERN-EDGED METAL-PLANE RESONANCE-SUPPRESSION
- Publication number 20200314999
- Publication date Oct 1, 2020
- Stephen Harvey Hall
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CRYSTAL OSCILLATOR INTERCONNECT ARCHITECTURE WITH NOISE IMMUNITY
- Publication number 20200274491
- Publication date Aug 27, 2020
- Intel Corporation
- Khang Choong YONG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH DENSITY FLEXIBLE INTERCONNECT DESIGN FOR MULTI-MODE SIGNALING
- Publication number 20200170113
- Publication date May 28, 2020
- Chaitanya Sreerama
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
STIFFENER AND PACKAGE SUBSTRATE FOR A SEMICONDUCTOR PACKAGE
- Publication number 20190311963
- Publication date Oct 10, 2019
- Intel Corporation
- Stephen CHRISTIANSON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE-LAYER, SELF-EQUALIZING INTERCONNECTS IN PACKAGE SUBSTRATES
- Publication number 20190214336
- Publication date Jul 11, 2019
- Intel Corporation
- Stephen Harvey Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MUTUAL INDUCTANCE SUPPRESSOR FOR CROSSTALK IMMUNITY ENHANCEMENT
- Publication number 20190215953
- Publication date Jul 11, 2019
- Intel Corporation
- Khang Choong YONG
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CRYSTAL OSCILLATOR INTERCONNECT ARCHITECTURE WITH NOISE IMMUNITY
- Publication number 20190158024
- Publication date May 23, 2019
- Intel Corporation
- Khang Choong YONG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRANSMISSION LINE DESIGN WITH ROUTING-OVER-VOID COMPENSATION
- Publication number 20190008029
- Publication date Jan 3, 2019
- Intel Corporation
- Khang Choong Yong
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ROUTING-OVER-VOID T-LINE COMPENSATION
- Publication number 20190007259
- Publication date Jan 3, 2019
- Intel Corporation
- Khang Choong Yong
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ELECTRICAL INTERCONNECT FOR A FLEXIBLE ELECTRONIC PACKAGE
- Publication number 20180350748
- Publication date Dec 6, 2018
- Intel Corporation
- Bok Eng Cheah
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CRYSTAL OSCILLATOR INTERCONNECT ARCHITECTURE WITH NOISE IMMUNITY
- Publication number 20180123514
- Publication date May 3, 2018
- Intel Corporation
- Khang Choong YONG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FLEXIBLE PRINTED CIRCUIT EMI ENCLOSURE
- Publication number 20170290154
- Publication date Oct 5, 2017
- Khang Choong Yong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM TO PROVIDE TACTILE FEEDBACK DURING NON-CONTACT INTERACTION
- Publication number 20170285745
- Publication date Oct 5, 2017
- Intel Corporation
- KEVIN J. DORAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC-BASED DECODER FOR CROSSTALK-HARNESSED SIGNALING
- Publication number 20170154007
- Publication date Jun 1, 2017
- Intel Corporation
- Chaitanya Sreerama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE CIRCUIT STRUCTURES FOR HIGH-BANDWIDTH COMMUNICATION
- Publication number 20160380326
- Publication date Dec 29, 2016
- Stephen H. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS, SYSTEM AND METHOD TO PROTECT SIGNAL COMMUNICATION INTEGRITY
- Publication number 20160174362
- Publication date Jun 16, 2016
- Kevin J. Doran
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
ELECTRICAL INTERCONNECT FOR AN ELECTRONIC PACKAGE
- Publication number 20160148866
- Publication date May 26, 2016
- Khang Choong Yong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MODE SELECTIVE BALANCED ENCODED INTERCONNECT
- Publication number 20160026597
- Publication date Jan 28, 2016
- Intel Corporation
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK AWARE DECODING FOR A DATA BUS
- Publication number 20140181348
- Publication date Jun 26, 2014
- Olufemi B. Oluwafemi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK AWARE DECODING FOR A DATA BUS
- Publication number 20140181358
- Publication date Jun 26, 2014
- Chaitanya Sreerama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK AWARE ENCODING FOR A DATA BUS
- Publication number 20140181357
- Publication date Jun 26, 2014
- Stephen H. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHIFTED SEGMENT LAYOUT FOR DIFFERENTIAL SIGNAL TRACES TO MITIGATE B...
- Publication number 20100202118
- Publication date Aug 12, 2010
- Tao Liang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Quasi-waveguide printed circuit board structure
- Publication number 20090080832
- Publication date Mar 26, 2009
- Intel Corporation
- Bryce D. Horine
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Interference mitigation
- Publication number 20090002952
- Publication date Jan 1, 2009
- Ralph Mesmer
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS

Stephen H. Hall

Person

Patents Grantslast 30 patents

Self-equalized and self-crosstalk-compensated 3D transmission line...

Pattern-edged metal-plane resonance-suppression

Stiffener and package substrate for a semiconductor package

Crystal oscillator interconnect architecture with noise immunity

Pattern-edged metal-plane resonance-suppression

Flexible printed circuit EMI enclosure

Multiple-layer, self-equalizing interconnects in package substrates

System to provide tactile feedback during non-contact interaction

Transmission line design with routing-over-void compensation

Mutual inductance suppressor for crosstalk immunity enhancement

Crystal oscillator interconnect architecture with noise immunity

Routing-over-void-T-line-compensation

Electrical interconnect for a flexible electronic package

Crystal oscillator interconnect architecture with noise immunity

Mode selective balanced encoded interconnect

Logic-based decoder for crosstalk-harnessed signaling

Crosstalk aware decoding for a data bus

Electrical interconnect for an electronic package

Structures for edge-to-edge coupling with flexible circuitry

Crosstalk aware encoding for a data bus

Method of forming a high speed interconnect

Shifted segment layout for differential signal traces to mitigate b...

Ultra-high bandwidth interconnect for data transmission

Managing system clocks to reduce RFI

Shifted segment layout for differential signal traces to mitigate b...

Modular waveguide inteconnect

Flexible waveguide cable with coupling antennas for digital signals

Shifted segment layout for differential signal traces to mitigate b...

Flexible waveguide cable with a dielectric core

Method, apparatus, and system for parallel plate mode radial patter...

Patents Applicationslast 30 patents

ROTATING CIRCULAR WAVEGUIDE CHANNEL FOR FOLDABLE ELECTRONIC DEVICES

ENCODING DIFFERENTIAL SIGNALS FOR POWER AND NOISE REDUCTION

PATTERN-EDGED METAL-PLANE RESONANCE-SUPPRESSION

TECHNOLOGIES FOR A LOW-NOISE-GENERATING INDUCTOR

TWISTED DIFFERENTIAL COMPENSATION FOR ROUTING HIGH-SPEED SIGNALS NE...

SELF-EQUALIZED AND SELF-CROSSTALK-COMPENSATED 3D TRANSMISSION LINE...

PATTERN-EDGED METAL-PLANE RESONANCE-SUPPRESSION

CRYSTAL OSCILLATOR INTERCONNECT ARCHITECTURE WITH NOISE IMMUNITY

HIGH DENSITY FLEXIBLE INTERCONNECT DESIGN FOR MULTI-MODE SIGNALING

STIFFENER AND PACKAGE SUBSTRATE FOR A SEMICONDUCTOR PACKAGE

MULTIPLE-LAYER, SELF-EQUALIZING INTERCONNECTS IN PACKAGE SUBSTRATES

MUTUAL INDUCTANCE SUPPRESSOR FOR CROSSTALK IMMUNITY ENHANCEMENT

CRYSTAL OSCILLATOR INTERCONNECT ARCHITECTURE WITH NOISE IMMUNITY

TRANSMISSION LINE DESIGN WITH ROUTING-OVER-VOID COMPENSATION

ROUTING-OVER-VOID T-LINE COMPENSATION

ELECTRICAL INTERCONNECT FOR A FLEXIBLE ELECTRONIC PACKAGE

CRYSTAL OSCILLATOR INTERCONNECT ARCHITECTURE WITH NOISE IMMUNITY

FLEXIBLE PRINTED CIRCUIT EMI ENCLOSURE

SYSTEM TO PROVIDE TACTILE FEEDBACK DURING NON-CONTACT INTERACTION

LOGIC-BASED DECODER FOR CROSSTALK-HARNESSED SIGNALING

FLEXIBLE CIRCUIT STRUCTURES FOR HIGH-BANDWIDTH COMMUNICATION

APPARATUS, SYSTEM AND METHOD TO PROTECT SIGNAL COMMUNICATION INTEGRITY

ELECTRICAL INTERCONNECT FOR AN ELECTRONIC PACKAGE

MODE SELECTIVE BALANCED ENCODED INTERCONNECT

CROSSTALK AWARE DECODING FOR A DATA BUS

CROSSTALK AWARE DECODING FOR A DATA BUS

CROSSTALK AWARE ENCODING FOR A DATA BUS

SHIFTED SEGMENT LAYOUT FOR DIFFERENTIAL SIGNAL TRACES TO MITIGATE B...

Quasi-waveguide printed circuit board structure

Interference mitigation