Stephen P. Horne

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Device input modes with corresponding cover configurations
- Patent number 9,645,721
- Issue date May 9, 2017
- Apple Inc.
- Stephen C Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for protecting integrated circuits from security attacks
- Patent number 9,405,917
- Issue date Aug 2, 2016
- Apple Inc.
- Stephen C Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory including a reduced leakage wordline driver
- Patent number 8,837,226
- Issue date Sep 16, 2014
- Apple Inc.
- Edward M. McCombs
- G11 - INFORMATION STORAGE
Information Patent Grant
Minimizing transistor size in integrated circuits
- Patent number 7,026,691
- Issue date Apr 11, 2006
- Advanced Micro Devices, Inc.
- Craig S. Sander
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for a 1 of N signal
- Patent number 6,911,846
- Issue date Jun 28, 2005
- Intrinsity, Inc.
- James S. Blomgren
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic logic scan gate method and apparatus
- Patent number 6,745,357
- Issue date Jun 1, 2004
- Intrinsity, Inc.
- David W. Chrudimsky
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Generation of route rules
- Patent number 6,732,346
- Issue date May 4, 2004
- Intrinsity, Inc.
- Stephen C. Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a N-NARY logic circuit using capacitance i...
- Patent number 6,571,378
- Issue date May 27, 2003
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for calculating dynamic logic block propagation delay target...
- Patent number 6,445,213
- Issue date Sep 3, 2002
- Intrinsity, Inc.
- Gopal Vijayan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for scan of synchronized dynamic logic using e...
- Patent number 6,415,405
- Issue date Jul 2, 2002
- Intrinsity, Inc.
- Stephen C. Horne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for a special stress mode for N-NARY logic tha...
- Patent number 6,412,085
- Issue date Jun 25, 2002
- Intrinsity, Inc.
- Stephen C. Horne
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for generating clock signals
- Patent number 6,288,589
- Issue date Sep 11, 2001
- Intrinsity, Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimizing transistor size in integrated circuits
- Patent number 6,287,953
- Issue date Sep 11, 2001
- Advanced Micro Devices, Inc.
- Craig S. Sander
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic logic scan gate method and apparatus
- Patent number 6,271,683
- Issue date Aug 7, 2001
- Intrinsity, Inc.
- Stephen C. Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for logic synchronization
- Patent number 6,268,746
- Issue date Jul 31, 2001
- Intrinsity, Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an N-NARY logic circuit
- Patent number 6,252,425
- Issue date Jun 26, 2001
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus that allows the logic state of a logic gate to...
- Patent number 6,233,707
- Issue date May 15, 2001
- Intrinsity, Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming minimal size spaces in integrated circuit conductive lines
- Patent number 6,191,034
- Issue date Feb 20, 2001
- Advanced Micro Devices
- Richard K. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for a RAM circuit having N-Nary output interface
- Patent number 6,181,596
- Issue date Jan 30, 2001
- Intrinsity, Inc.
- Stephen C. Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimizing transistor size in integrated circuits
- Patent number 6,146,954
- Issue date Nov 14, 2000
- Advanced Micro Devices, Inc.
- Richard K. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for a N-nary logic circuit using capacitance i...
- Patent number 6,124,735
- Issue date Sep 26, 2000
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for logic synchronization
- Patent number 6,118,304
- Issue date Sep 12, 2000
- Intrinsity, Inc.
- Terence M. Potter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for an address triggered RAM circuit
- Patent number 6,118,716
- Issue date Sep 12, 2000
- Evsx, Inc.
- Stephen C. Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for multi-bit register cell
- Patent number 6,115,294
- Issue date Sep 5, 2000
- Evsx, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a logic circuit with constant power consum...
- Patent number 6,107,835
- Issue date Aug 22, 2000
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for 1 of 4 register file design
- Patent number 6,104,642
- Issue date Aug 15, 2000
- Intrinsity, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a N-nary logic circuit using 1 of N signals
- Patent number 6,069,497
- Issue date May 30, 2000
- Evsx, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a RAM circuit having N-nary word line gene...
- Patent number 6,069,836
- Issue date May 30, 2000
- Evsx, Inc.
- Stephen C. Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a N-nary logic circuit using 1 of 4 signals
- Patent number 6,066,965
- Issue date May 23, 2000
- Evsx, Inc.
- James S. Blomgren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming local interconnects in integrated circuits
- Patent number 6,051,881
- Issue date Apr 18, 2000
- Advanced Micro Devices
- Richard K. Klein
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MECHANISM FOR PROTECTING INTEGRATED CIRCUITS FROM SECURITY ATTACKS
- Publication number 20150347762
- Publication date Dec 3, 2015
- Apple Inc.
- Stephen C. Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE INPUT MODES WITH CORRESPONDING USER INTERFACES
- Publication number 20150026623
- Publication date Jan 22, 2015
- Apple Inc.
- Stephen C. Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY INCLUDING A REDUCED LEAKAGE WORDLINE DRIVER
- Publication number 20130111130
- Publication date May 2, 2013
- Edward M. McCombs
- G11 - INFORMATION STORAGE
Information Patent Application
Generation of route rules
- Publication number 20020178428
- Publication date Nov 28, 2002
- Stephen C. Horne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CALCULATING DYNAMIC LOGIC BLOCK PROPAGATION DELAY TARGET...
- Publication number 20020067187
- Publication date Jun 6, 2002
- Intrinsity, Inc.
- Gopal Vijayan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic logic scan gate method and apparatus
- Publication number 20010039635
- Publication date Nov 8, 2001
- David W. Chrudimsky
- H03 - BASIC ELECTRONIC CIRCUITRY

Stephen P. Horne

Person

Patents Grantslast 30 patents

Device input modes with corresponding cover configurations

Mechanism for protecting integrated circuits from security attacks

Memory including a reduced leakage wordline driver

Minimizing transistor size in integrated circuits

Method and apparatus for a 1 of N signal

Dynamic logic scan gate method and apparatus

Generation of route rules

Method and apparatus for a N-NARY logic circuit using capacitance i...

Method for calculating dynamic logic block propagation delay target...

Method and apparatus for scan of synchronized dynamic logic using e...

Method and apparatus for a special stress mode for N-NARY logic tha...

Method and apparatus for generating clock signals

Minimizing transistor size in integrated circuits

Dynamic logic scan gate method and apparatus

Method and apparatus for logic synchronization

Method and apparatus for an N-NARY logic circuit

Method and apparatus that allows the logic state of a logic gate to...

Forming minimal size spaces in integrated circuit conductive lines

Method and apparatus for a RAM circuit having N-Nary output interface

Minimizing transistor size in integrated circuits

Method and apparatus for a N-nary logic circuit using capacitance i...

Method and apparatus for logic synchronization

Method and apparatus for an address triggered RAM circuit

Method and apparatus for multi-bit register cell

Method and apparatus for a logic circuit with constant power consum...

Method and apparatus for 1 of 4 register file design

Method and apparatus for a N-nary logic circuit using 1 of N signals

Method and apparatus for a RAM circuit having N-nary word line gene...

Method and apparatus for a N-nary logic circuit using 1 of 4 signals

Forming local interconnects in integrated circuits

Patents Applicationslast 30 patents

MECHANISM FOR PROTECTING INTEGRATED CIRCUITS FROM SECURITY ATTACKS

DEVICE INPUT MODES WITH CORRESPONDING USER INTERFACES

MEMORY INCLUDING A REDUCED LEAKAGE WORDLINE DRIVER

Generation of route rules

METHOD FOR CALCULATING DYNAMIC LOGIC BLOCK PROPAGATION DELAY TARGET...

Dynamic logic scan gate method and apparatus