Steve PRINS

Person

Fairview, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
IC with matched thin film resistors
- Patent number 11,522,043
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Scott William Jessen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly gate extension design methodology to improve CMOS performance...
- Patent number 11,251,093
- Issue date Feb 15, 2022
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly gate extension design methodology to improve CMOS performance...
- Patent number 10,734,290
- Issue date Aug 4, 2020
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly gate extension design methodology to improve CMOS performance...
- Patent number 10,134,643
- Issue date Nov 20, 2018
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SRAM well-tie with an uninterrupted grated first poly and first con...
- Patent number 9,741,724
- Issue date Aug 22, 2017
- Texas Instruments Incorporated
- Anand Seshadri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly gate extension design methodology to improve CMOS performance...
- Patent number 9,583,488
- Issue date Feb 28, 2017
- Texas Instruments Incorporated
- Younsung Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alignment to multiple layers
- Patent number 9,343,332
- Issue date May 17, 2016
- Texas Instruments Incorporated
- Thomas John Aton
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
SRAM well-tie with an uninterrupted grated first poly and first con...
- Patent number 9,209,195
- Issue date Dec 8, 2015
- Texas Instruments Incorporated
- Anand Seshadri
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alignment to multiple layers
- Patent number 9,117,775
- Issue date Aug 25, 2015
- Texas Instruments Incorporated
- Thomas John Aton
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Context protection for a column interleaved memory
- Patent number 8,971,084
- Issue date Mar 3, 2015
- Texas Instruments Incorporated
- Lakshmikantha Holla
- G11 - INFORMATION STORAGE
Information Patent Grant
Curvature reduction for semiconductor wafers
- Patent number 8,252,609
- Issue date Aug 28, 2012
- Texas Instruments Incorporated
- Brian K. Kirkpatrick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer planarity control between pattern levels
- Patent number 8,216,945
- Issue date Jul 10, 2012
- Texas Instruments Incorporated
- Steven L. Prins
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of achieving dense-pitch interconnect patterning in integrat...
- Patent number 7,790,525
- Issue date Sep 7, 2010
- Texas Instruments Incorporated
- Steven Lee Prins
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
THIN FILM RESISTOR MISMATCH IMPROVEMENT USING A SELF-ALIGNED DOUBLE...
- Publication number 20240113156
- Publication date Apr 4, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Scott William JESSEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC WITH MATCHED THIN FILM RESISTORS
- Publication number 20210134939
- Publication date May 6, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Scott William Jessen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...
- Publication number 20200350210
- Publication date Nov 5, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...
- Publication number 20190057904
- Publication date Feb 21, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...
- Publication number 20170133273
- Publication date May 11, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CON...
- Publication number 20160049410
- Publication date Feb 18, 2016
- TEXAS INSTRUMENTS INCORPORATED
- Anand SESHADRI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALIGNMENT TO MULTIPLE LAYERS
- Publication number 20150325472
- Publication date Nov 12, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Thomas John ATON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...
- Publication number 20150187768
- Publication date Jul 2, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Younsung CHOI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTEXT PROTECTION FOR A COLUMN INTERLEAVED MEMORY
- Publication number 20150029773
- Publication date Jan 29, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Lakshmikantha Holla
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CON...
- Publication number 20140327082
- Publication date Nov 6, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Anand SESHADRI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALIGNMENT TO MULTIPLE LAYERS
- Publication number 20120302059
- Publication date Nov 29, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Thomas John ATON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CURVATURE REDUCTION FOR SEMICONDUCTOR WAFERS
- Publication number 20100261298
- Publication date Oct 14, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Brian K. Kirkpatrick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER PLANARITY CONTROL BETWEEN PATTERN LEVELS
- Publication number 20100261353
- Publication date Oct 14, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Steven L. Prins
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method of Achieving Dense-Pitch Interconnect Patterning in Integrat...
- Publication number 20090101983
- Publication date Apr 23, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Steven Lee Prins
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD TO FORM CMOS CIRCUITS WITH SUB 50NM STI STRUCTURES USING SEL...
- Publication number 20090096055
- Publication date Apr 16, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Clint L. Montgomery
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to Form CMOS Circuits Using Optimized Sidewalls
- Publication number 20090098702
- Publication date Apr 16, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Brian K. Kirkpatrick
- H01 - BASIC ELECTRIC ELEMENTS

Steve PRINS

Person

Patents Grantslast 30 patents

IC with matched thin film resistors

Poly gate extension design methodology to improve CMOS performance...

Poly gate extension design methodology to improve CMOS performance...

Poly gate extension design methodology to improve CMOS performance...

SRAM well-tie with an uninterrupted grated first poly and first con...

Poly gate extension design methodology to improve CMOS performance...

Alignment to multiple layers

SRAM well-tie with an uninterrupted grated first poly and first con...

Alignment to multiple layers

Context protection for a column interleaved memory

Curvature reduction for semiconductor wafers

Wafer planarity control between pattern levels

Method of achieving dense-pitch interconnect patterning in integrat...

Patents Applicationslast 30 patents

THIN FILM RESISTOR MISMATCH IMPROVEMENT USING A SELF-ALIGNED DOUBLE...

IC WITH MATCHED THIN FILM RESISTORS

POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...

POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...

POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...

SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CON...

ALIGNMENT TO MULTIPLE LAYERS

POLY GATE EXTENSION DESIGN METHODOLOGY TO IMPROVE CMOS PERFORMANCE...

CONTEXT PROTECTION FOR A COLUMN INTERLEAVED MEMORY

SRAM WELL-TIE WITH AN UNINTERRUPTED GRATED FIRST POLY AND FIRST CON...

ALIGNMENT TO MULTIPLE LAYERS

CURVATURE REDUCTION FOR SEMICONDUCTOR WAFERS

WAFER PLANARITY CONTROL BETWEEN PATTERN LEVELS

Method of Achieving Dense-Pitch Interconnect Patterning in Integrat...

METHOD TO FORM CMOS CIRCUITS WITH SUB 50NM STI STRUCTURES USING SEL...

Method to Form CMOS Circuits Using Optimized Sidewalls