Steven Caranci

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Toronto, CA

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Patents Grantslast 30 patents

Information Patent Grant
Generation of readable hierarchical path identifiers
- Patent number 8,661,329
- Issue date Feb 25, 2014
- Altera Corporation
- Mark Ari Teper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing automated timing closure analys...
- Patent number 8,504,970
- Issue date Aug 6, 2013
- Altera Corporation
- Shawn Malhotra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphical block-based design exploration tool
- Patent number 8,407,645
- Issue date Mar 26, 2013
- Altera Corporation
- Steven Caranci
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance visualization of delay in circuit design
- Patent number 7,657,857
- Issue date Feb 2, 2010
- Altera Corporation
- Przemek Guzy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for designing systems using logic regions
- Patent number 7,197,734
- Issue date Mar 27, 2007
- Altera Corporation
- Deshanand P. Singh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Performance Visualization of Delay in Circuit Design
- Publication number 20080216034
- Publication date Sep 4, 2008
- Altera Corporation
- Przemek Guzy
- G06 - COMPUTING CALCULATING COUNTING