Steven Craig Barner

Person

Shrewsbury, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Secure low-latency chip-to-chip communication
- Patent number 12,061,729
- Issue date Aug 13, 2024
- Marvell Asia Pte, Ltd.
- Georgios Angelopoulos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure low-latency chip-to-chip communication
- Patent number 10,872,173
- Issue date Dec 22, 2020
- Marvell Asia Pte, Ltd.
- Georgios Angelopoulos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low latency interconnect protocol for coherent multi-chip communica...
- Patent number 10,592,452
- Issue date Mar 17, 2020
- Cavium, LLC
- Steven C. Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic data rate matching
- Patent number 9,933,809
- Issue date Apr 3, 2018
- Cavium, Inc.
- Steven C. Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bypass FIFO for multiple virtual channels
- Patent number 9,824,058
- Issue date Nov 21, 2017
- Cavium, Inc.
- Steven C. Barner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Look-aside processor unit with internal and external access for mul...
- Patent number 9,491,099
- Issue date Nov 8, 2016
- Cavium, Inc.
- Wilson Parkhurst Snyder
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Partitioned error code computation
- Patent number 9,471,416
- Issue date Oct 18, 2016
- Cavium, Inc.
- Steven C. Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System on chip link layer protocol
- Patent number 9,432,288
- Issue date Aug 30, 2016
- Cavium, Inc.
- Steven C. Barner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for enabling access to a protected hardware resource
- Patent number 8,544,106
- Issue date Sep 24, 2013
- Cavium, Inc.
- Amer Haider
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Secure Low-latency Chip-to-Chip Communication
- Publication number 20210081572
- Publication date Mar 18, 2021
- Georgios Angelopoulos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure Low-latency Chip-to-Chip Communication
- Publication number 20200097681
- Publication date Mar 26, 2020
- Cavium, LLC
- Georgios Angelopoulos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW LATENCY INTERCONNECT PROTOCOL FOR COHERENT MULTI-CHIP COMMUNICA...
- Publication number 20200081857
- Publication date Mar 12, 2020
- Steven C. Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bypass FIFO for Multiple Virtual Channels
- Publication number 20160139880
- Publication date May 19, 2016
- Cavium, Inc.
- Steven C. Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC DATA RATE MATCHING
- Publication number 20160139622
- Publication date May 19, 2016
- Cavium, Inc.
- Steven C. Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONED ERROR CODE COMPUTATION
- Publication number 20150248323
- Publication date Sep 3, 2015
- Cavium, Inc.
- Steven C. Barner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ON CHIP LINK LAYER PROTOCOL
- Publication number 20150249602
- Publication date Sep 3, 2015
- Cavium, Inc.
- Steven C. Barner
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOOK-ASIDE PROCESSOR UNIT WITH INTERNAL AND EXTERNAL ACCESS FOR MUL...
- Publication number 20150188816
- Publication date Jul 2, 2015
- Cavium, Inc.
- Wilson Parkhurst Snyder
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR ENABLING ACCESS TO A PROTECTED HARDWARE RESOURCE
- Publication number 20120027199
- Publication date Feb 2, 2012
- CAVIUM NETWORKS
- Amer Haider
- G06 - COMPUTING CALCULATING COUNTING

Steven Craig Barner

Person

Patents Grantslast 30 patents

Secure low-latency chip-to-chip communication

Secure low-latency chip-to-chip communication

Low latency interconnect protocol for coherent multi-chip communica...

Automatic data rate matching

Bypass FIFO for multiple virtual channels

Look-aside processor unit with internal and external access for mul...

Partitioned error code computation

System on chip link layer protocol

System and method for enabling access to a protected hardware resource

Patents Applicationslast 30 patents

Secure Low-latency Chip-to-Chip Communication

Secure Low-latency Chip-to-Chip Communication

LOW LATENCY INTERCONNECT PROTOCOL FOR COHERENT MULTI-CHIP COMMUNICA...

Bypass FIFO for Multiple Virtual Channels

AUTOMATIC DATA RATE MATCHING

PARTITIONED ERROR CODE COMPUTATION

SYSTEM ON CHIP LINK LAYER PROTOCOL

LOOK-ASIDE PROCESSOR UNIT WITH INTERNAL AND EXTERNAL ACCESS FOR MUL...

SYSTEM AND METHOD FOR ENABLING ACCESS TO A PROTECTED HARDWARE RESOURCE