Steven D. Millman

Person

Mesa, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of modeling circuit cells with distributed serial loads
- Patent number 6,374,203
- Issue date Apr 16, 2002
- Motorola, Inc.
- Steven D. Millman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method of encrypting key validation
- Patent number 5,631,962
- Issue date May 20, 1997
- Motorola, Inc.
- Thomas J. Balph
- G07 - CHECKING-DEVICES
Information Patent Grant
Low power flip-flop circuit and method thereof
- Patent number 5,498,988
- Issue date Mar 12, 1996
- Motorola, Inc.
- Alberto J. Reyes
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test pattern fault equivalence
- Patent number 5,410,548
- Issue date Apr 25, 1995
- Motorola, Inc.
- Steven D. Millman
- G01 - MEASURING TESTING
Information Patent Grant
Technique and method for asynchronous scan design
- Patent number 5,406,216
- Issue date Apr 11, 1995
- Motorola, Inc.
- Steven D. Millman
- G01 - MEASURING TESTING
Information Patent Grant
Test pattern generation
- Patent number 5,390,193
- Issue date Feb 14, 1995
- Motorola, Inc.
- Steven D. Millman
- G01 - MEASURING TESTING
Information Patent Grant
Pulsed CMOS logic circuit having selectable rise and fall times
- Patent number 5,128,555
- Issue date Jul 7, 1992
- Motorola, Inc.
- Steven D. Millman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Transmission gate having a pass transistor with feedback
- Patent number 5,126,596
- Issue date Jun 30, 1992
- Motorola, Inc.
- Steven D. Millman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bidirectional buffer having tri-state buffers for circuit isolation
- Patent number 5,107,148
- Issue date Apr 21, 1992
- Motorola, Inc.
- Steven D. Millman
- G01 - MEASURING TESTING

Steven D. Millman

Person

Patents Grantslast 30 patents

Method of modeling circuit cells with distributed serial loads

Circuit and method of encrypting key validation

Low power flip-flop circuit and method thereof

Test pattern fault equivalence

Technique and method for asynchronous scan design

Test pattern generation

Pulsed CMOS logic circuit having selectable rise and fall times

Transmission gate having a pass transistor with feedback

Bidirectional buffer having tri-state buffers for circuit isolation