Steven Lee Gregor

Person

Owego, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory view for non-volatile memory module
- Patent number 11,971,818
- Issue date Apr 30, 2024
- Cadence Design Systems, Inc.
- Steven L. Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control algorithm generator for non-volatile memory module
- Patent number 11,966,633
- Issue date Apr 23, 2024
- Cadence Design Systems, Inc.
- Steven L. Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation event reduction and power control during MBIST through c...
- Patent number 10,783,299
- Issue date Sep 22, 2020
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing for memory error correction code logic
- Patent number 10,706,950
- Issue date Jul 7, 2020
- Cadence Design Systems, Inc.
- Patrick Gallagher
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing for memories during mission mode self-test
- Patent number 10,706,952
- Issue date Jul 7, 2020
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
System, method and computer-accessible medium for automated identif...
- Patent number 10,699,795
- Issue date Jun 30, 2020
- Cadence Design Systems, Inc.
- Norman Card
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Failing read count diagnostics for memory built-in self-test
- Patent number 10,593,419
- Issue date Mar 17, 2020
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
On demand data stream controller for programming and executing oper...
- Patent number 10,541,043
- Issue date Jan 21, 2020
- Cadence Design Systems, Inc.
- Carl Alexander Wisnesky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-channel, programmable fuse control unit
- Patent number 10,504,607
- Issue date Dec 10, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic diagnostics analysis for memory built-in self-test
- Patent number 10,482,989
- Issue date Nov 19, 2019
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Register-transfer level design engineering change order strategy
- Patent number 10,395,747
- Issue date Aug 27, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and computer-readable media utilizing improved da...
- Patent number 10,387,599
- Issue date Aug 20, 2019
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying results in simulation through simulation add-on to suppor...
- Patent number 10,387,598
- Issue date Aug 20, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Customizable built-in self-test testplans for memory units
- Patent number 10,319,459
- Issue date Jun 11, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Test logic at register transfer level in an integrated circuit design
- Patent number 10,192,013
- Issue date Jan 29, 2019
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory built-in self-test logic in an integrated circuit design
- Patent number 10,095,822
- Issue date Oct 9, 2018
- Cadence Design Systems, Inc.
- Navneet Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated method identifying physical memories within a core or mac...
- Patent number 10,007,489
- Issue date Jun 26, 2018
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing error correction code (ECC) logic...
- Patent number 9,865,362
- Issue date Jan 9, 2018
- Cadence Design Systems, Inc.
- Puneet Arora
- G11 - INFORMATION STORAGE
Information Patent Grant
Power domain aware insertion methods and designs for testing and re...
- Patent number 9,640,280
- Issue date May 2, 2017
- Cadence Design Systems, Inc.
- Puneet Arora
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for optimizing memory-built-in-self test
- Patent number 8,990,749
- Issue date Mar 24, 2015
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing memory-built-in-self test
- Patent number 8,719,761
- Issue date May 6, 2014
- Candence Design Systems, Inc.
- Norman Card
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low cost production testing for memory
- Patent number 8,677,196
- Issue date Mar 18, 2014
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault modeling for state retention logic
- Patent number 8,296,703
- Issue date Oct 23, 2012
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing state retention logic in low power systems
- Patent number 8,271,226
- Issue date Sep 18, 2012
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G01 - MEASURING TESTING
Information Patent Grant
Programable multi-port memory BIST with compact microcode
- Patent number 7,168,005
- Issue date Jan 23, 2007
- Cadence Design Systems, Inc.
- R. Dean Adams
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing multi-port memories
- Patent number 7,032,144
- Issue date Apr 18, 2006
- Cadence Design Systems Inc.
- R. Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-dimensional redundancy calculation
- Patent number 7,003,704
- Issue date Feb 21, 2006
- International Business Machines Corporation
- R. Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self test system and method for two-dimensional memory red...
- Patent number 6,907,554
- Issue date Jun 14, 2005
- International Business Machines Corporation
- R. Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
System initialization of microcode-based memory built-in self-test
- Patent number 6,874,111
- Issue date Mar 29, 2005
- International Business Machines Corporation
- R. Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable memory built-in self-test combining microcode and fini...
- Patent number 6,651,201
- Issue date Nov 18, 2003
- International Business Machines Corporation
- R. Dean Adams
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Optimizing Memory-Built-In-Self Test
- Publication number 20140089874
- Publication date Mar 27, 2014
- Cadence Design Systems, Inc.
- Norman Card
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Optimizing Memory-Built-In-Self Test
- Publication number 20140089875
- Publication date Mar 27, 2014
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS
- Publication number 20090326854
- Publication date Dec 31, 2009
- Cadence Design Systems, Inc.
- Krishna CHAKRAVADHANULA
- G01 - MEASURING TESTING
Information Patent Application
BUILT-IN SELF TEST SYSTEM AND METHOD FOR TWO-DIMENSIONAL MEMORY RED...
- Publication number 20040225939
- Publication date Nov 11, 2004
- International Business Machines Corporation
- R. Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Two-dimensional redundancy calculation
- Publication number 20040093540
- Publication date May 13, 2004
- International Business Machines Corporation
- R. Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for testing multi-port memories
- Publication number 20040006727
- Publication date Jan 8, 2004
- Cadence Design Systems, Inc.
- R. Dean Adams
- G11 - INFORMATION STORAGE
Information Patent Application
Programable multi-port memory bist with compact microcode
- Publication number 20030120974
- Publication date Jun 26, 2003
- Cadence Design Systems, Inc.
- R. Dean Adams
- G06 - COMPUTING CALCULATING COUNTING

Steven Lee Gregor

Person

Patents Grantslast 30 patents

Memory view for non-volatile memory module

Control algorithm generator for non-volatile memory module

Simulation event reduction and power control during MBIST through c...

Testing for memory error correction code logic

Testing for memories during mission mode self-test

System, method and computer-accessible medium for automated identif...

Failing read count diagnostics for memory built-in self-test

On demand data stream controller for programming and executing oper...

Multiple-channel, programmable fuse control unit

Dynamic diagnostics analysis for memory built-in self-test

Register-transfer level design engineering change order strategy

Systems, methods, and computer-readable media utilizing improved da...

Verifying results in simulation through simulation add-on to suppor...

Customizable built-in self-test testplans for memory units

Test logic at register transfer level in an integrated circuit design

Memory built-in self-test logic in an integrated circuit design

Automated method identifying physical memories within a core or mac...

Method and apparatus for testing error correction code (ECC) logic...

Power domain aware insertion methods and designs for testing and re...

Method and apparatus for optimizing memory-built-in-self test

Method and apparatus for optimizing memory-built-in-self test

Low cost production testing for memory

Fault modeling for state retention logic

Testing state retention logic in low power systems

Programable multi-port memory BIST with compact microcode

Method and apparatus for testing multi-port memories

Two-dimensional redundancy calculation

Built-in self test system and method for two-dimensional memory red...

System initialization of microcode-based memory built-in self-test

Programmable memory built-in self-test combining microcode and fini...

Patents Applicationslast 30 patents

Method and Apparatus for Optimizing Memory-Built-In-Self Test

Method and Apparatus for Optimizing Memory-Built-In-Self Test

TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS

BUILT-IN SELF TEST SYSTEM AND METHOD FOR TWO-DIMENSIONAL MEMORY RED...

Two-dimensional redundancy calculation

Method and apparatus for testing multi-port memories

Programable multi-port memory bist with compact microcode