Steven P. Young

Person

Boulder, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compute dataflow architecture
- Patent number 11,750,195
- Issue date Sep 5, 2023
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compute dataflow architecture
- Patent number 11,451,230
- Issue date Sep 20, 2022
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power delivery network for active-on-active stacked integrated circ...
- Patent number 11,270,977
- Issue date Mar 8, 2022
- Xilinx, Inc.
- Praful Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip stacked devices
- Patent number 11,239,203
- Issue date Feb 1, 2022
- Xilinx, Inc.
- Brian C. Gaide
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Redundancy scheme for multi-chip stacked devices
- Patent number 10,825,772
- Issue date Nov 3, 2020
- Steven P. Young
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Configurable logic block (CLB) internal routing architecture for en...
- Patent number 10,715,149
- Issue date Jul 14, 2020
- Xilinx, Inc.
- Eric F. Dellinger
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Distributed multi-die routing in a multi-chip module
- Patent number 9,859,896
- Issue date Jan 2, 2018
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Lut cascading circuit
- Patent number 9,602,108
- Issue date Mar 21, 2017
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interconnect multiplexers and methods of reducing contention curren...
- Patent number 9,509,307
- Issue date Nov 29, 2016
- Xilinx, Inc.
- Vikram Santurkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits for and methods of controlling power within an integrated...
- Patent number 9,438,244
- Issue date Sep 6, 2016
- Xilinx, Inc.
- Santosh Kumar Sood
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Signed multiplier circuit utilizing a uniform array of logic blocks
- Patent number 9,411,554
- Issue date Aug 9, 2016
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two gate pitch FPGA memory cell
- Patent number 9,177,634
- Issue date Nov 3, 2015
- Xilinx, Inc.
- Steven P. Young
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to reduce power segmentation overhead within a...
- Patent number 9,058,454
- Issue date Jun 16, 2015
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits for shifting bussed data
- Patent number 9,002,915
- Issue date Apr 7, 2015
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock network architecture
- Patent number 8,937,491
- Issue date Jan 20, 2015
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for programmable device testing in stacked die...
- Patent number 8,933,447
- Issue date Jan 13, 2015
- Xilinx, Inc.
- Arifur Rahman
- G01 - MEASURING TESTING
Information Patent Grant
Programmable interconnect network
- Patent number 8,773,164
- Issue date Jul 8, 2014
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-timed single track circuit
- Patent number 8,773,166
- Issue date Jul 8, 2014
- Xilinx, Inc.
- Brian C. Gaide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplier circuits with optional shift function
- Patent number 8,706,793
- Issue date Apr 22, 2014
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration of a multi-die integrated circuit
- Patent number 8,536,895
- Issue date Sep 17, 2013
- Xilinx, Inc.
- Weiguang Lu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplier architecture utilizing a uniform array of logic blocks,...
- Patent number 8,527,572
- Issue date Sep 3, 2013
- Xilinx, Inc.
- Steven P. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable device with dynamic DSP architecture
- Patent number 8,495,122
- Issue date Jul 23, 2013
- Xilinx, Inc.
- James M. Simkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error checking parity and syndrome of a block of data with relocate...
- Patent number 8,301,988
- Issue date Oct 30, 2012
- Xilinx, Inc.
- Warren E. Cory
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hybrid integrated circuit device
- Patent number 8,293,547
- Issue date Oct 23, 2012
- Xilinx, Inc.
- James Karp
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Error checking parity and syndrome of a block of data with relocate...
- Patent number 8,245,102
- Issue date Aug 14, 2012
- Xilinx, Inc.
- Warren E. Cory
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable integrated circuit with mirrored interconnect structure
- Patent number 8,120,382
- Issue date Feb 21, 2012
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuration of a multi-die integrated circuit
- Patent number 8,058,897
- Issue date Nov 15, 2011
- Xilinx, Inc.
- Weiguang Lu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock distribution to facilitate gated clocks
- Patent number 8,058,905
- Issue date Nov 15, 2011
- Xilinx, Inc.
- Matthew H. Klein
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Methods of implementing and modeling interconnect lines at optional...
- Patent number 8,001,511
- Issue date Aug 16, 2011
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bus-based logic blocks with optional constant input
- Patent number 7,982,496
- Issue date Jul 19, 2011
- Xilinx, Inc.
- Steven P. Young
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
COMPUTE DATAFLOW ARCHITECTURE
- Publication number 20220368330
- Publication date Nov 17, 2022
- Xilinx, Inc.
- Steven P. YOUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTE DATAFLOW ARCHITECTURE
- Publication number 20210336622
- Publication date Oct 28, 2021
- Xilinx, Inc.
- Steven P. YOUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER DELIVERY NETWORK FOR ACTIVE-ON-ACTIVE STACKED INTEGRATED CIRC...
- Publication number 20210143127
- Publication date May 13, 2021
- Xilinx, Inc.
- Praful JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP STACKED DEVICES
- Publication number 20210134760
- Publication date May 6, 2021
- Xilinx, Inc.
- Brian C. GAIDE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUNDANCY SCHEME FOR MULTI-CHIP STACKED DEVICES
- Publication number 20200303311
- Publication date Sep 24, 2020
- Xilinx, Inc.
- Steven P. YOUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUITS FOR AND METHODS OF CONTROLLING POWER WITHIN AN INTEGRATED...
- Publication number 20160118988
- Publication date Apr 28, 2016
- Xilinx, Inc.
- Santosh Kumar Sood
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK NETWORK ARCHITECTURE
- Publication number 20140132305
- Publication date May 15, 2014
- Xilinx, Inc.
- Brian C. Gaide
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION OF A MULTI-DIE INTEGRATED CIRCUIT
- Publication number 20120019292
- Publication date Jan 26, 2012
- Xilinx, Inc.
- Weiguang Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUIT WITH MIRRORED INTERCONNECT STRUCTURE
- Publication number 20110215834
- Publication date Sep 8, 2011
- Xilinx, Inc.
- Trevor J. Bauer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HYBRID INTEGRATED CIRCUIT DEVICE
- Publication number 20110147949
- Publication date Jun 23, 2011
- Xilinx, Inc.
- James Karp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Formation of a hybrid integrated circuit device
- Publication number 20090160482
- Publication date Jun 25, 2009
- Xilinx, Inc.
- James Karp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCO...
- Publication number 20090121737
- Publication date May 14, 2009
- Xilinx, Inc.
- Xiao-Jie Yuan
- G01 - MEASURING TESTING
Information Patent Application
Columnar floorplan
- Publication number 20070035330
- Publication date Feb 15, 2007
- Xilinx, Inc.
- Steven P. Young
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20070013428
- Publication date Jan 18, 2007
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20060290403
- Publication date Dec 28, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic device having an embedded differential clock tree
- Publication number 20060290402
- Publication date Dec 28, 2006
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Characterizing circuit performance by separating device and interco...
- Publication number 20060267618
- Publication date Nov 30, 2006
- Xilinx, Inc.
- Xiao-Jie Yuan
- G01 - MEASURING TESTING
Information Patent Application
Differential clock tree in an integrated circuit
- Publication number 20050242865
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic device having an embedded differential clock tree
- Publication number 20050242866
- Publication date Nov 3, 2005
- Xilinx, Inc.
- Vasisht Mantra Vadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Characterizing circuit performance by separating device and interco...
- Publication number 20050149777
- Publication date Jul 7, 2005
- Xilinx, Inc.
- Xiao-Jie Yuan
- G01 - MEASURING TESTING
Information Patent Application
Programmable logic device with pipelined DSP slices
- Publication number 20050144211
- Publication date Jun 30, 2005
- Xilinx, Inc.
- James M. Simkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic device with dynamic DSP architecture
- Publication number 20050144210
- Publication date Jun 30, 2005
- Xilinx, Inc.
- James M. Simkins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Arithmetic circuit with multiplexed addend inputs
- Publication number 20050144216
- Publication date Jun 30, 2005
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic device with cascading DSP slices
- Publication number 20050144212
- Publication date Jun 30, 2005
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mathematical circuit with dynamic rounding
- Publication number 20050144213
- Publication date Jun 30, 2005
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Applications of cascading DSP slices
- Publication number 20050144215
- Publication date Jun 30, 2005
- Xilinx, Inc.
- James M. Simkins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable gate array and embedded circuitry initialization and p...
- Publication number 20050040850
- Publication date Feb 24, 2005
- Xilinx, Inc.
- David P. Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Columnar architecture
- Publication number 20050007155
- Publication date Jan 13, 2005
- Xilinx, Inc.
- Steven P. Young
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Columnar floorplan
- Publication number 20050007147
- Publication date Jan 13, 2005
- Xilinx, Inc.
- Steven P. Young
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit with interface tile for coupling to a stacked-di...
- Publication number 20040268286
- Publication date Dec 30, 2004
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY

Steven P. Young

Person

Patents Grantslast 30 patents

Compute dataflow architecture

Compute dataflow architecture

Power delivery network for active-on-active stacked integrated circ...

Multi-chip stacked devices

Redundancy scheme for multi-chip stacked devices

Configurable logic block (CLB) internal routing architecture for en...

Distributed multi-die routing in a multi-chip module

Lut cascading circuit

Interconnect multiplexers and methods of reducing contention curren...

Circuits for and methods of controlling power within an integrated...

Signed multiplier circuit utilizing a uniform array of logic blocks

Two gate pitch FPGA memory cell

Method and apparatus to reduce power segmentation overhead within a...

Circuits for shifting bussed data

Clock network architecture

Method and apparatus for programmable device testing in stacked die...

Programmable interconnect network

Self-timed single track circuit

Multiplier circuits with optional shift function

Configuration of a multi-die integrated circuit

Multiplier architecture utilizing a uniform array of logic blocks,...

Programmable device with dynamic DSP architecture

Error checking parity and syndrome of a block of data with relocate...

Hybrid integrated circuit device

Error checking parity and syndrome of a block of data with relocate...

Programmable integrated circuit with mirrored interconnect structure

Configuration of a multi-die integrated circuit

Clock distribution to facilitate gated clocks

Methods of implementing and modeling interconnect lines at optional...

Bus-based logic blocks with optional constant input

Patents Applicationslast 30 patents

COMPUTE DATAFLOW ARCHITECTURE

COMPUTE DATAFLOW ARCHITECTURE

POWER DELIVERY NETWORK FOR ACTIVE-ON-ACTIVE STACKED INTEGRATED CIRC...

MULTI-CHIP STACKED DEVICES

REDUNDANCY SCHEME FOR MULTI-CHIP STACKED DEVICES

CIRCUITS FOR AND METHODS OF CONTROLLING POWER WITHIN AN INTEGRATED...

CLOCK NETWORK ARCHITECTURE

CONFIGURATION OF A MULTI-DIE INTEGRATED CIRCUIT

PROGRAMMABLE INTEGRATED CIRCUIT WITH MIRRORED INTERCONNECT STRUCTURE

HYBRID INTEGRATED CIRCUIT DEVICE

Formation of a hybrid integrated circuit device

CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCO...

Columnar floorplan

Differential clock tree in an integrated circuit

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Characterizing circuit performance by separating device and interco...

Differential clock tree in an integrated circuit

Programmable logic device having an embedded differential clock tree

Characterizing circuit performance by separating device and interco...

Programmable logic device with pipelined DSP slices

Programmable logic device with dynamic DSP architecture

Arithmetic circuit with multiplexed addend inputs

Programmable logic device with cascading DSP slices

Mathematical circuit with dynamic rounding

Applications of cascading DSP slices

Programmable gate array and embedded circuitry initialization and p...

Columnar architecture

Columnar floorplan

Integrated circuit with interface tile for coupling to a stacked-di...