Steven R. Ferguson

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Granite Shoals, TX, US

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Patents Grantslast 30 patents

Information Patent Grant
Multiple uses for BIST test latches
- Patent number 8,006,153
- Issue date Aug 23, 2011
- International Business Machines Corporation
- Steven Ross Ferguson
- G01 - MEASURING TESTING
Information Patent Grant
Testing functional boundary logic at asynchronous clock boundaries...
- Patent number 7,908,536
- Issue date Mar 15, 2011
- International Business Machines Corporation
- Nathan P. Chelstrom
- G01 - MEASURING TESTING
Information Patent Grant
Multiple uses for BIST test latches
- Patent number 7,574,642
- Issue date Aug 11, 2009
- International Business Machines Corporation
- Steven Ross Ferguson
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing an integrated circuit device having elements wit...
- Patent number 7,500,164
- Issue date Mar 3, 2009
- International Business Machines Corporation
- Nathan P. Chelstrom
- G01 - MEASURING TESTING
Information Patent Grant
Method for testing functional boundary logic at asynchronous clock...
- Patent number 7,478,300
- Issue date Jan 13, 2009
- International Business Machines Corporation
- Nathan P. Chelstrom
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for reducing power consumption in a processor...
- Patent number 7,233,188
- Issue date Jun 19, 2007
- Sony Computer Entertainment Inc.
- Chiaki Takano
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Testing Functional Boundary Logic at Asynchronous Clock Boundaries...
- Publication number 20090083594
- Publication date Mar 26, 2009
- International Business Machines Corporation
- Nathan P. Chelstrom
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLE USES FOR BIST TEST LATCHES
- Publication number 20080313512
- Publication date Dec 18, 2008
- Steven Ross Ferguson
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT DEVICE HAVING E...
- Publication number 20070283205
- Publication date Dec 6, 2007
- Nathan P. Chelstrom
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR TESTING FUNCTIONAL BOUNDARY LOGIC AT ASYNCHRO...
- Publication number 20070266284
- Publication date Nov 15, 2007
- Nathan P. Chelstrom
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS FOR REDUCING POWER CONSUMPTION IN A PROCESSOR...
- Publication number 20070146037
- Publication date Jun 28, 2007
- Sony Computer Entertainment Inc.
- Chiaki Takano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple uses for bist test latches
- Publication number 20060242519
- Publication date Oct 26, 2006
- Steven Ross Ferguson
- G01 - MEASURING TESTING