Steven Tu

Person

Phoenix, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Implementing direct access caches in coherent multiprocessors
- Patent number 8,533,401
- Issue date Sep 10, 2013
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Video block memory read request translation and tagging
- Patent number 8,265,169
- Issue date Sep 11, 2012
- Intel Corporation
- Steven Tu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital image decoder with integrated concurrent image prescaler
- Patent number 8,111,932
- Issue date Feb 7, 2012
- Intel Corporation
- Steven J. Tu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Test access port
- Patent number 8,065,576
- Issue date Nov 22, 2011
- Intel Corporation
- David E. Miner
- G01 - MEASURING TESTING
Information Patent Grant
Power optimized replay of blocked operations in a pipilined archite...
- Patent number 7,966,477
- Issue date Jun 21, 2011
- Marvell International Ltd.
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital image decoder with integrated concurrent image prescaler
- Patent number 7,957,603
- Issue date Jun 7, 2011
- Intel Corporation
- Steven Tu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelining techniques for deinterlacing video information
- Patent number 7,952,643
- Issue date May 31, 2011
- Intel Corporation
- Satyajit Mohapatra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelining techniques for deinterlacing video information
- Patent number 7,944,502
- Issue date May 17, 2011
- Intel Corporation
- Satyajit Mohapatra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transactional flow management interrupt debug architecture
- Patent number 7,890,790
- Issue date Feb 15, 2011
- Intel Corporation
- Steven Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Spatio-temporal adaptive video de-interlacing for parallel processing
- Patent number 7,804,542
- Issue date Sep 28, 2010
- Intel Corporation
- Jorge E. Caviedes
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method for arbitrating heterogeneous agents in on-chi...
- Patent number 7,765,349
- Issue date Jul 27, 2010
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing line writes in cache coherent s...
- Patent number 7,757,046
- Issue date Jul 13, 2010
- Intel Corporation
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for power optimized replay via selective recir...
- Patent number 7,725,683
- Issue date May 25, 2010
- Marvell International Ltd.
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory to support a processor's power mode of operation
- Patent number 7,685,379
- Issue date Mar 23, 2010
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing heterogeneous interconnects
- Patent number 7,640,387
- Issue date Dec 29, 2009
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and apparatus for early fixed latency subtractive decoding
- Patent number 7,634,603
- Issue date Dec 15, 2009
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test access port
- Patent number 7,627,797
- Issue date Dec 1, 2009
- Intel Corporation
- David E. Miner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transactional flow management interrupt debug architecture
- Patent number 7,620,840
- Issue date Nov 17, 2009
- Intel Corporation
- Steven Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory to support a processor's power mode of operation
- Patent number 7,487,299
- Issue date Feb 3, 2009
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for supporting opportunistic sharing in cohere...
- Patent number 7,464,227
- Issue date Dec 9, 2008
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for shared resource management in a multiproce...
- Patent number 7,464,208
- Issue date Dec 9, 2008
- Intel Corporation
- Steven Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for controlling access to shared resources in...
- Patent number 7,428,732
- Issue date Sep 23, 2008
- Intel Corporation
- Jason Sandri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for arbitrating heterogeneous agents in on-chi...
- Patent number 7,428,607
- Issue date Sep 23, 2008
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and apparatus for early fixed latency subtractive decoding
- Patent number 7,406,553
- Issue date Jul 29, 2008
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for early fixed latency subtractive decoding in...
- Patent number 7,406,552
- Issue date Jul 29, 2008
- Marvell International, Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory to support a processor's power mode of operation
- Patent number 7,404,043
- Issue date Jul 22, 2008
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pushing of clean data to one or more processors in a system having...
- Patent number 7,366,845
- Issue date Apr 29, 2008
- Intel Corporation
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing heterogeneous interconnects
- Patent number 7,353,317
- Issue date Apr 1, 2008
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory to support a processor's power mode of operation
- Patent number 7,290,093
- Issue date Oct 30, 2007
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power/performance optimized cache using memory write prevention thr...
- Patent number 7,234,028
- Issue date Jun 19, 2007
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MULTI-TENANCY PROTECTION FOR ACCELERATORS
- Publication number 20240396711
- Publication date Nov 28, 2024
- Intel Corporation
- Akshay Kadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TENANCY PROTECTION FOR ACCELERATORS
- Publication number 20220311594
- Publication date Sep 29, 2022
- Intel Corporation
- Akshay Kadam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIERED ACCESS TO REGIONS OF INTEREST IN VIDEO FRAMES
- Publication number 20210152530
- Publication date May 20, 2021
- Praveen Prasad Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR MEMORY-EFFICIENT VIDEO ENCODING AND DECODING
- Publication number 20210120259
- Publication date Apr 22, 2021
- Intel Corporation
- Praveen P. Nair
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIGITAL IMAGE DECODER WITH INTEGRATED CONCURRENT IMAGE PRESCALER
- Publication number 20110200308
- Publication date Aug 18, 2011
- Steven Tu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PIPELINING TECHNIQUES FOR DEINTERLACING VIDEO INFORMATION
- Publication number 20100220232
- Publication date Sep 2, 2010
- Satyajit Mohapatra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TEST ACCESS PORT
- Publication number 20100050019
- Publication date Feb 25, 2010
- David E. Miner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSACTIONAL FLOW MANAGEMENT INTERRUPT DEBUG ARCHITECTURE
- Publication number 20100023808
- Publication date Jan 28, 2010
- Steven Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Apparatus for Early Fixed Latency Subtractive Decoding
- Publication number 20080282008
- Publication date Nov 13, 2008
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING HETEROGENEOUS INTERCONNECTS
- Publication number 20080250168
- Publication date Oct 9, 2008
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Video block memory read request translation and tagging
- Publication number 20080159405
- Publication date Jul 3, 2008
- Steven Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transactional flow management interrupt debug architecture
- Publication number 20080162757
- Publication date Jul 3, 2008
- Steven Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Image memory tiling
- Publication number 20080158601
- Publication date Jul 3, 2008
- Steven Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital image decoder with integrated concurrent image prescaler
- Publication number 20080159654
- Publication date Jul 3, 2008
- Steven Tu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Spatio-temporal adaptive video de-interlacing for parallel processing
- Publication number 20080002055
- Publication date Jan 3, 2008
- Jorge E. Caviedes
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelining techniques for deinterlacing video information
- Publication number 20070229704
- Publication date Oct 4, 2007
- Satyajit Mohapatra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND APPARATUS FOR EARLY FIXED LATENCY SUBTRACTIVE DECODING
- Publication number 20070186019
- Publication date Aug 9, 2007
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for fixed latency subtractive decoding
- Publication number 20070162672
- Publication date Jul 12, 2007
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for supporting heterogeneous agents in on-chip...
- Publication number 20060271716
- Publication date Nov 30, 2006
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test access port
- Publication number 20060248426
- Publication date Nov 2, 2006
- David E. Miner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for implementing heterogeneous interconnects
- Publication number 20060143358
- Publication date Jun 29, 2006
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for shared resource management in a multiproce...
- Publication number 20060136925
- Publication date Jun 22, 2006
- Steven Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for pushing data to a processor cache
- Publication number 20060112238
- Publication date May 25, 2006
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Direct processor cache access within a system having a coherent mul...
- Publication number 20060004961
- Publication date Jan 5, 2006
- Steven J. Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Direct processor cache access within a system having a coherent mul...
- Publication number 20060004965
- Publication date Jan 5, 2006
- Steven J. Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pushing of clean data to one or more processors in a system having...
- Publication number 20050289303
- Publication date Dec 29, 2005
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for supporting heterogeneous agents in on-chip...
- Publication number 20050216632
- Publication date Sep 29, 2005
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache memory to support a processor's power mode of operation
- Publication number 20050204195
- Publication date Sep 15, 2005
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache memory to support a processor's power mode of operation
- Publication number 20050204202
- Publication date Sep 15, 2005
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache memory to support a processor's power mode of operation
- Publication number 20050193176
- Publication date Sep 1, 2005
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Implementing direct access caches in coherent multiprocessors

Video block memory read request translation and tagging

Digital image decoder with integrated concurrent image prescaler

Test access port

Power optimized replay of blocked operations in a pipilined archite...

Digital image decoder with integrated concurrent image prescaler

Pipelining techniques for deinterlacing video information

Pipelining techniques for deinterlacing video information

Transactional flow management interrupt debug architecture

Spatio-temporal adaptive video de-interlacing for parallel processing

Apparatus and method for arbitrating heterogeneous agents in on-chi...

Method and apparatus for optimizing line writes in cache coherent s...

Apparatus and method for power optimized replay via selective recir...

Cache memory to support a processor's power mode of operation

Method and apparatus for implementing heterogeneous interconnects

System and apparatus for early fixed latency subtractive decoding

Test access port

Transactional flow management interrupt debug architecture

Cache memory to support a processor's power mode of operation

Method and apparatus for supporting opportunistic sharing in cohere...

Method and apparatus for shared resource management in a multiproce...

Method and apparatus for controlling access to shared resources in...

Apparatus and method for arbitrating heterogeneous agents in on-chi...

System and apparatus for early fixed latency subtractive decoding

Systems and methods for early fixed latency subtractive decoding in...

Cache memory to support a processor's power mode of operation

Pushing of clean data to one or more processors in a system having...

Method and apparatus for implementing heterogeneous interconnects

Cache memory to support a processor's power mode of operation

Power/performance optimized cache using memory write prevention thr...

Patents Applicationslast 30 patents

MULTI-TENANCY PROTECTION FOR ACCELERATORS

MULTI-TENANCY PROTECTION FOR ACCELERATORS

TIERED ACCESS TO REGIONS OF INTEREST IN VIDEO FRAMES

TECHNOLOGIES FOR MEMORY-EFFICIENT VIDEO ENCODING AND DECODING

DIGITAL IMAGE DECODER WITH INTEGRATED CONCURRENT IMAGE PRESCALER

PIPELINING TECHNIQUES FOR DEINTERLACING VIDEO INFORMATION

TEST ACCESS PORT

TRANSACTIONAL FLOW MANAGEMENT INTERRUPT DEBUG ARCHITECTURE

System and Apparatus for Early Fixed Latency Subtractive Decoding

METHOD AND APPARATUS FOR IMPLEMENTING HETEROGENEOUS INTERCONNECTS

Video block memory read request translation and tagging

Transactional flow management interrupt debug architecture

Image memory tiling

Digital image decoder with integrated concurrent image prescaler

Spatio-temporal adaptive video de-interlacing for parallel processing

Pipelining techniques for deinterlacing video information

SYSTEM AND APPARATUS FOR EARLY FIXED LATENCY SUBTRACTIVE DECODING

Method and apparatus for fixed latency subtractive decoding

Apparatus and method for supporting heterogeneous agents in on-chip...

Test access port

Method and apparatus for implementing heterogeneous interconnects

Method and apparatus for shared resource management in a multiproce...

Techniques for pushing data to a processor cache

Direct processor cache access within a system having a coherent mul...

Direct processor cache access within a system having a coherent mul...

Pushing of clean data to one or more processors in a system having...

Apparatus and method for supporting heterogeneous agents in on-chip...

Cache memory to support a processor's power mode of operation

Cache memory to support a processor's power mode of operation

Cache memory to support a processor's power mode of operation