Stuart Auvinen

Person

Santa Cruz, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Software programmable edge delay for SRAM write enable signals on d...
- Patent number 5,802,548
- Issue date Sep 1, 1998
- Chips & Technologies, Inc.
- Stuart T. Auvinen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RAM based FIFO memory half-full detection apparatus and method
- Patent number 5,490,257
- Issue date Feb 6, 1996
- Advanced Micro Devices, Inc.
- Barry A. Hoberman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data cache management system with test mode using index registers a...
- Patent number 5,276,833
- Issue date Jan 4, 1994
- Chips & Technologies, Inc.
- Stuart T. Auvinen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for use of expanded memory system (EMS) to acc...
- Patent number 5,271,098
- Issue date Dec 14, 1993
- Chips & Technologies, Inc.
- Rashid N. Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-aligned DRAM state machine for page-mode DRAM control
- Patent number 5,210,856
- Issue date May 11, 1993
- Chips & Technologies, Inc.
- Stuart Auvinen
- G11 - INFORMATION STORAGE
Information Patent Grant
Biasing scheme for FIFO memories
- Patent number 4,975,879
- Issue date Dec 4, 1990
- Advanced Micro Devices, Inc.
- Stuart T. Auvinen
- G11 - INFORMATION STORAGE
Information Patent Grant
Interleaved sensing system for FIFO and burst-mode memories
- Patent number 4,954,987
- Issue date Sep 4, 1990
- Advanced Micro Devices, Inc.
- Stuart T. Auvinen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast flush for a first-in first-out memory
- Patent number 4,802,122
- Issue date Jan 31, 1989
- Advanced Micro Devices, Inc.
- Stuart T. Auvinen
- G06 - COMPUTING CALCULATING COUNTING

Stuart Auvinen

Person

Patents Grantslast 30 patents

Software programmable edge delay for SRAM write enable signals on d...

RAM based FIFO memory half-full detection apparatus and method

Data cache management system with test mode using index registers a...

Method and apparatus for use of expanded memory system (EMS) to acc...

Non-aligned DRAM state machine for page-mode DRAM control

Biasing scheme for FIFO memories

Interleaved sensing system for FIFO and burst-mode memories

Fast flush for a first-in first-out memory