Stuart E. Sailer

Person

Campbell, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Processing ordered data requests to a memory
- Patent number 6,725,339
- Issue date Apr 20, 2004
- Intel Corporation
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing temporal and non-temporal data in...
- Patent number 6,542,966
- Issue date Apr 1, 2003
- Intel Corporation
- John Crawford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for processing cache misses
- Patent number 6,438,650
- Issue date Aug 20, 2002
- Intel Corporation
- Nhon T. Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical fully-associative-translation lookaside buffer structure
- Patent number 6,418,521
- Issue date Jul 9, 2002
- Intel Corporation
- Gregory S. Mathews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing ordered data requests to a memory
- Patent number 6,381,678
- Issue date Apr 30, 2002
- Intel Corporation
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-ported, pipelined, two level cache system
- Patent number 6,272,597
- Issue date Aug 7, 2001
- Intel Corporation
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically deferring transactions
- Patent number 5,761,444
- Issue date Jun 2, 1998
- Intel Corporation
- Jasmin Ajanovic
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Processing ordered data requests to a memory
- Publication number 20020073284
- Publication date Jun 13, 2002
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING ORDERED DATA REQUESTS TO A MEMORY
- Publication number 20010044881
- Publication date Nov 22, 2001
- JOHN WAI CHEONG FU
- G06 - COMPUTING CALCULATING COUNTING

Stuart E. Sailer

Person

Patents Grantslast 30 patents

Processing ordered data requests to a memory

Method and apparatus for managing temporal and non-temporal data in...

Method and apparatus for processing cache misses

Hierarchical fully-associative-translation lookaside buffer structure

Processing ordered data requests to a memory

Dual-ported, pipelined, two level cache system

Method and apparatus for dynamically deferring transactions

Patents Applicationslast 30 patents

Processing ordered data requests to a memory

PROCESSING ORDERED DATA REQUESTS TO A MEMORY