Subarnarekha Sinha

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Distance metric for accurate lithographic hotspot classification us...
- Patent number 9,098,649
- Issue date Aug 4, 2015
- Synopsys, Inc.
- Charles C. Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accurate process hotspot detection using critical design rule extra...
- Patent number 8,601,419
- Issue date Dec 3, 2013
- Synopsys, Inc.
- Charles C. Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pattern-clip-based hotspot database system for layout verification
- Patent number 8,578,313
- Issue date Nov 5, 2013
- Synopsys, Inc.
- Zongwu Tang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Dual-purpose perturbation engine for automatically processing patte...
- Patent number 8,566,754
- Issue date Oct 22, 2013
- Synopsys, Inc.
- Kent Y. Kwang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Distance metric for accurate lithographic hotspot classification us...
- Patent number 8,490,030
- Issue date Jul 16, 2013
- Synopsys, Inc.
- Charles C. Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Range pattern matching for hotspots containing vias and incompletel...
- Patent number 8,452,075
- Issue date May 28, 2013
- Synopsys, Inc.
- Jingyu Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Range pattern definition of susceptibility of layout regions to fab...
- Patent number 8,219,941
- Issue date Jul 10, 2012
- Synopsys, Inc.
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying layout regions susceptible to fabrication issues by usi...
- Patent number 8,209,639
- Issue date Jun 26, 2012
- Synopsys, Inc.
- Subarnarekha Sinha
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Fast evaluation of average critical area for IC layouts
- Patent number 8,205,179
- Issue date Jun 19, 2012
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast evaluation of average critical area for IC layouts
- Patent number 8,205,185
- Issue date Jun 19, 2012
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for identifying and correcting phase conflicts
- Patent number 8,141,007
- Issue date Mar 20, 2012
- Synopsys, Inc.
- Subarnarekha Sinha
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method and system for facilitating floorplanning for 3D IC
- Patent number 8,006,212
- Issue date Aug 23, 2011
- Synopsys, Inc.
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicting IC manufacturing yield by considering both systematic an...
- Patent number 8,000,826
- Issue date Aug 16, 2011
- Synopsys, Inc.
- Jianfeng Luo
- G05 - CONTROLLING REGULATING
Information Patent Grant
Fast evaluation of average critical area for ic layouts
- Patent number 7,962,873
- Issue date Jun 14, 2011
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast evaluation of average critical area for IC layouts
- Patent number 7,962,882
- Issue date Jun 14, 2011
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Range pattern definition of susceptibility of layout regions to fab...
- Patent number 7,703,067
- Issue date Apr 20, 2010
- Synopsys, Inc.
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electrostatic-discharge protection using a micro-electromechanical-...
- Patent number 7,679,872
- Issue date Mar 16, 2010
- Synopsys, Inc.
- Jamil Kawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus to reduce random yield loss
- Patent number 7,543,255
- Issue date Jun 2, 2009
- Synopsys, Inc.
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dummy filling technique for improved planarization of chip surface...
- Patent number 7,509,622
- Issue date Mar 24, 2009
- Synopsys, Inc.
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying layout regions susceptible to fabrication issues by usi...
- Patent number 7,503,029
- Issue date Mar 10, 2009
- Synopsys, Inc.
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for identifying and correcting phase conflicts
- Patent number 7,496,883
- Issue date Feb 24, 2009
- Synopsys, Inc.
- Subarnarekha Sinha
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Fast evaluation of average critical area for IC layouts
- Patent number 7,346,865
- Issue date Mar 18, 2008
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Distance Metric For Accurate Lithographic Hotspot Classification Us...
- Publication number 20130326435
- Publication date Dec 5, 2013
- Charles C. Chiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FACILITATING FLOORPLANNING FOR 3D IC
- Publication number 20100031217
- Publication date Feb 4, 2010
- Synopsys, Inc.
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTROSTATIC-DISCHARGE PROTECTION USING A MICRO-ELECTROMECHANICAL-...
- Publication number 20100014199
- Publication date Jan 21, 2010
- Synopsys, Inc.
- Jamil Kawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS
- Publication number 20090307641
- Publication date Dec 10, 2009
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS
- Publication number 20090307644
- Publication date Dec 10, 2009
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PATTERN-CLIP-BASED HOTSPOT DATABASE SYSTEM FOR LAYOUT VERIFICATION
- Publication number 20090271749
- Publication date Oct 29, 2009
- Synopsys, Inc.
- Zongwu Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-PURPOSE PERTURBATION ENGINE FOR AUTOMATICALLY PROCESSING PATTE...
- Publication number 20090268958
- Publication date Oct 29, 2009
- Synopsys, Inc.
- Kent Y. Kwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IDENTIFYING AND CORRECTING PHASE CONFLICTS
- Publication number 20090150850
- Publication date Jun 11, 2009
- Synopsys, Inc.
- Subarnarekha Sinha
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
IDENTIFYING LAYOUT REGIONS SUSCEPTIBLE TO FABRICATION ISSUES BY USI...
- Publication number 20090138835
- Publication date May 28, 2009
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RANGE PATTERN DEFINITION OF SUSCEPTIBILITY OF LAYOUT REGIONS TO FAB...
- Publication number 20090132980
- Publication date May 21, 2009
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Range pattern matching for hotspots containing vias and incompletel...
- Publication number 20080253644
- Publication date Oct 16, 2008
- Jingyu Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC
- Publication number 20080216028
- Publication date Sep 4, 2008
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC
- Publication number 20080148196
- Publication date Jun 19, 2008
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dummy Filling Technique For Improved Planarization Of Chip Surface...
- Publication number 20070245284
- Publication date Oct 18, 2007
- Synopsys Inc.
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Range pattern definition of susceptibility of layout regions to fab...
- Publication number 20070240086
- Publication date Oct 11, 2007
- SYNOPSYS, INC.
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Identifying layout regions susceptible to fabrication issues by usi...
- Publication number 20070234246
- Publication date Oct 4, 2007
- SYNOPSYS, INC.
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to reduce random yield loss
- Publication number 20070192751
- Publication date Aug 16, 2007
- Subarnarekha Sinha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Predicting IC manufacturing yield by considering both systematic an...
- Publication number 20070174797
- Publication date Jul 26, 2007
- Jianfeng Luo
- G05 - CONTROLLING REGULATING
Information Patent Application
Method and apparatus for identifying and correcting phase conflicts
- Publication number 20060199083
- Publication date Sep 7, 2006
- Subarnarekha Sinha
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Fast evaluation of average critical area for IC layouts
- Publication number 20060095877
- Publication date May 4, 2006
- Synopsys, Inc.
- Qing Su
- G06 - COMPUTING CALCULATING COUNTING

Subarnarekha Sinha

Person

Patents Grantslast 30 patents

Distance metric for accurate lithographic hotspot classification us...

Accurate process hotspot detection using critical design rule extra...

Pattern-clip-based hotspot database system for layout verification

Dual-purpose perturbation engine for automatically processing patte...

Distance metric for accurate lithographic hotspot classification us...

Range pattern matching for hotspots containing vias and incompletel...

Range pattern definition of susceptibility of layout regions to fab...

Identifying layout regions susceptible to fabrication issues by usi...

Fast evaluation of average critical area for IC layouts

Fast evaluation of average critical area for IC layouts

Method and apparatus for identifying and correcting phase conflicts

Method and system for facilitating floorplanning for 3D IC

Predicting IC manufacturing yield by considering both systematic an...

Fast evaluation of average critical area for ic layouts

Fast evaluation of average critical area for IC layouts

Range pattern definition of susceptibility of layout regions to fab...

Electrostatic-discharge protection using a micro-electromechanical-...

Method and apparatus to reduce random yield loss

Dummy filling technique for improved planarization of chip surface...

Identifying layout regions susceptible to fabrication issues by usi...

Method and apparatus for identifying and correcting phase conflicts

Fast evaluation of average critical area for IC layouts

Patents Applicationslast 30 patents

Distance Metric For Accurate Lithographic Hotspot Classification Us...

METHOD AND SYSTEM FOR FACILITATING FLOORPLANNING FOR 3D IC

ELECTROSTATIC-DISCHARGE PROTECTION USING A MICRO-ELECTROMECHANICAL-...

FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS

FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS

PATTERN-CLIP-BASED HOTSPOT DATABASE SYSTEM FOR LAYOUT VERIFICATION

DUAL-PURPOSE PERTURBATION ENGINE FOR AUTOMATICALLY PROCESSING PATTE...

METHOD AND APPARATUS FOR IDENTIFYING AND CORRECTING PHASE CONFLICTS

IDENTIFYING LAYOUT REGIONS SUSCEPTIBLE TO FABRICATION ISSUES BY USI...

RANGE PATTERN DEFINITION OF SUSCEPTIBILITY OF LAYOUT REGIONS TO FAB...

Range pattern matching for hotspots containing vias and incompletel...

FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC

FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC

Dummy Filling Technique For Improved Planarization Of Chip Surface...

Range pattern definition of susceptibility of layout regions to fab...

Identifying layout regions susceptible to fabrication issues by usi...

Method and apparatus to reduce random yield loss

Predicting IC manufacturing yield by considering both systematic an...

Method and apparatus for identifying and correcting phase conflicts

Fast evaluation of average critical area for IC layouts