Subbarao Arumilli

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low-latency signaling-link retimer
- Patent number 12,143,288
- Issue date Nov 12, 2024
- Astera Labs, Inc.
- Casey Morrison
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Capacity-expanding memory control component
- Patent number 12,095,480
- Issue date Sep 17, 2024
- Astera Labs, Inc.
- Enrique Musoll
- G11 - INFORMATION STORAGE
Information Patent Grant
Capacity-expanding memory control component
- Patent number 12,061,793
- Issue date Aug 13, 2024
- Astera Labs, Inc.
- Enrique Musoll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metadata-caching integrated circuit device
- Patent number 12,032,479
- Issue date Jul 9, 2024
- Astera Labs, Inc.
- Enrique Musoll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retimer with mesochronous intra-lane path controllers
- Patent number 12,003,610
- Issue date Jun 4, 2024
- Astera Labs, Inc.
- Enrique Musoll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retimer with path-coordinated flow-rate compensation
- Patent number 11,949,629
- Issue date Apr 2, 2024
- Astera Labs, Inc.
- Enrique Musoll
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low-latency retimer with seamless clock switchover
- Patent number 11,853,115
- Issue date Dec 26, 2023
- Astera Labs, Inc.
- Jitendra Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capacity-expanding memory control component
- Patent number 11,722,152
- Issue date Aug 8, 2023
- Astera Labs, Inc.
- Enrique Musoll
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-latency retimer with seamless clock switchover
- Patent number 11,487,317
- Issue date Nov 1, 2022
- Astera Labs, Inc.
- Jitendra Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retimer with mesochronous intra-lane path controllers
- Patent number 11,424,905
- Issue date Aug 23, 2022
- Astera Labs, Inc.
- Enrique Musoll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retimer with path-coordinated flow-rate compensation
- Patent number 11,349,626
- Issue date May 31, 2022
- Astera Labs, Inc.
- Enrique Musoll
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable-aggregation retimer with media-dedicated controllers
- Patent number 11,327,913
- Issue date May 10, 2022
- Astera Labs, Inc.
- Casey Morrison
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-latency signaling-link retimer
- Patent number 11,258,696
- Issue date Feb 22, 2022
- Asiera Labs, Inc.
- Casey Morrison
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low-latency retimer with seamless clock switchover
- Patent number 11,150,687
- Issue date Oct 19, 2021
- Astera Labs, Inc.
- Jitendra Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow aware buffer management for data center switches
- Patent number 9,705,808
- Issue date Jul 11, 2017
- Cisco Technology, Inc.
- Subbarao Arumilli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-chip module with multiple interposers
- Patent number 9,337,120
- Issue date May 10, 2016
- Cisco Technology, Inc.
- Li Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-server consolidated input/output (IO) device
- Patent number 8,972,611
- Issue date Mar 3, 2015
- Cisco Technology, Inc.
- Michael B. Galles
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic flow redistribution for head of line blocking avoidance
- Patent number 8,565,092
- Issue date Oct 22, 2013
- Cisco Technology, Inc.
- Subbarao Arumilli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Forwarding multi-destination packets in a network with virtual port...
- Patent number 8,249,069
- Issue date Aug 21, 2012
- Cisco Technology, Inc.
- Pirabhu Raman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
METADATA-CACHING INTEGRATED CIRCUIT DEVICE
- Publication number 20240054072
- Publication date Feb 15, 2024
- Astera Labs, Inc.
- Enrique Musoll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flow Aware Buffer Management for Data Center Switches
- Publication number 20150271081
- Publication date Sep 24, 2015
- Cisco Technology, Inc.
- Subbarao Arumilli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Multi-Chip Module with Multiple Interposers
- Publication number 20140048928
- Publication date Feb 20, 2014
- Cisco Technology, Inc.
- Li Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-Server Consolidated Input/Output (IO) Device
- Publication number 20130042019
- Publication date Feb 14, 2013
- Cisco Technology, Inc.
- Michael B. Galles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Flow Segregation for Optimal Load Balancing Among Ports in...
- Publication number 20120307641
- Publication date Dec 6, 2012
- Cisco Technology, Inc.
- Subbarao Arumilli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dynamic Flow Redistribution for Head of Line Blocking Avoidance
- Publication number 20120127860
- Publication date May 24, 2012
- Cisco Technology, Inc.
- Subbarao Arumilli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Forwarding multi-destination packets in a network with virtual port...
- Publication number 20110243136
- Publication date Oct 6, 2011
- Cisco Technology, Inc.
- Pirabhu Raman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ETHERNET FORWARDING IN HIGH PERFORMANCE FABRICS
- Publication number 20080181243
- Publication date Jul 31, 2008
- Brocade Communications Systems, Inc.
- Suresh Vobbilisetty
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for virtualizing storage devices inside a stor...
- Publication number 20040028043
- Publication date Feb 12, 2004
- Brocade Communications Systems, Inc.
- Naveen S. Maveli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Subbarao Arumilli

Person

Patents Grantslast 30 patents

Low-latency signaling-link retimer

Capacity-expanding memory control component

Capacity-expanding memory control component

Metadata-caching integrated circuit device

Retimer with mesochronous intra-lane path controllers

Retimer with path-coordinated flow-rate compensation

Low-latency retimer with seamless clock switchover

Capacity-expanding memory control component

Low-latency retimer with seamless clock switchover

Retimer with mesochronous intra-lane path controllers

Retimer with path-coordinated flow-rate compensation

Configurable-aggregation retimer with media-dedicated controllers

Low-latency signaling-link retimer

Low-latency retimer with seamless clock switchover

Flow aware buffer management for data center switches

Multi-chip module with multiple interposers

Multi-server consolidated input/output (IO) device

Dynamic flow redistribution for head of line blocking avoidance

Forwarding multi-destination packets in a network with virtual port...

Patents Applicationslast 30 patents

METADATA-CACHING INTEGRATED CIRCUIT DEVICE

Flow Aware Buffer Management for Data Center Switches

Multi-Chip Module with Multiple Interposers

Multi-Server Consolidated Input/Output (IO) Device

Dynamic Flow Segregation for Optimal Load Balancing Among Ports in...

Dynamic Flow Redistribution for Head of Line Blocking Avoidance

Forwarding multi-destination packets in a network with virtual port...

ETHERNET FORWARDING IN HIGH PERFORMANCE FABRICS

Method and apparatus for virtualizing storage devices inside a stor...