Subhash Gupta

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Method of copper/copper surface bonding using a conducting polymer...
- Patent number 7,452,808
- Issue date Nov 18, 2008
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of copper/copper surface bonding using a conducting polymer...
- Patent number 7,060,613
- Issue date Jun 13, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of copper/copper surface bonding using a conducting polymer...
- Patent number 6,967,162
- Issue date Nov 22, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of copper/copper surface bonding using a conducting polymer...
- Patent number 6,821,888
- Issue date Nov 23, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Yakub Aliyu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods to clean copper contamination on wafer edge
- Patent number 6,813,796
- Issue date Nov 9, 2004
- Chartered Semiconductor
- Sudipto Ranendra Roy
- B08 - CLEANING
Information Patent Grant
Method to form copper interconnects by adding an aluminum layer to...
- Patent number 6,740,580
- Issue date May 25, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of using hydrogen plasma to pre-clean copper surfaces during...
- Patent number 6,720,204
- Issue date Apr 13, 2004
- Chartered Semiconductor Manufacturing Ltd.
- John Leonard Sudijono
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of application of conductive cap-layer in flip-chip, cob, an...
- Patent number 6,705,512
- Issue date Mar 16, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Kwok Keung Paul Ho
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for cleaning semiconductor structures using hydrocarbon and...
- Patent number 6,692,579
- Issue date Feb 17, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Sudipto Ranendra Roy
- C11 - ANIMAL AND VEGETABLE OILS, FATS, FATTY SUBSTANCES AND WAXES FATTY ACIDS...
Information Patent Grant
Method to create a copper diffusion deterrent interface
- Patent number 6,683,002
- Issue date Jan 27, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of extreme ultraviolet mask engineering
- Patent number 6,656,643
- Issue date Dec 2, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Subhash Gupta
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Method for stripping copper in damascene interconnects
- Patent number 6,565,664
- Issue date May 20, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Subhash Gupta
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Non-metallic barrier formations for copper damascene type interconn...
- Patent number 6,566,260
- Issue date May 20, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for removing contaminants from the perimeter o...
- Patent number 6,540,841
- Issue date Apr 1, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Sudipto Ranendra Roy
- B08 - CLEANING
Information Patent Grant
Non-metallic barrier formations for copper damascene type interconn...
- Patent number 6,531,390
- Issue date Mar 11, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-metallic barrier formations for copper damascene type interconn...
- Patent number 6,489,233
- Issue date Dec 3, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing embedded organic stop layer for dual damasc...
- Patent number 6,475,810
- Issue date Nov 5, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Mei Sheng Zhou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual layer pattern formation method for dual damascene interconnect
- Patent number 6,465,157
- Issue date Oct 15, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Jianxun Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite silicon-metal nitride barrier to prevent formation of met...
- Patent number 6,465,888
- Issue date Oct 15, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to create copper traps by modifying treatment on the dielect...
- Patent number 6,429,117
- Issue date Aug 6, 2002
- Chartered Semiconductor Manufacturing Ltd.
- John Sudijono
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non metallic barrier formations for copper damascene type interconn...
- Patent number 6,429,122
- Issue date Aug 6, 2002
- Chartered Semiconductor Manufacturing, Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of application of displacement reaction to form a conductive...
- Patent number 6,417,088
- Issue date Jul 9, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Kwok Keung Paul Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of application of copper solution in flip-chip, COB, and mic...
- Patent number 6,415,973
- Issue date Jul 9, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Kwok Keung Paul Ho
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for stripping copper in damascene interconnects
- Patent number 6,394,114
- Issue date May 28, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Subhash Gupta
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method to thin down copper barriers in deep submicron geometries by...
- Patent number 6,391,783
- Issue date May 21, 2002
- Chartered Semiconductor Manufacturing Ltd.
- John Sudijono
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to form self-aligned, L-shaped sidewall spacers
- Patent number 6,391,732
- Issue date May 21, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMP process utilizing dummy plugs in damascene process
- Patent number 6,380,087
- Issue date Apr 30, 2002
- Chartered Semiconductor Manufacturing Inc.
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of application of conductive cap-layer in flip-chip, COB, an...
- Patent number 6,378,759
- Issue date Apr 30, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Kwok Keung Paul Ho
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method to form high performance copper damascene interconnects by d...
- Patent number 6,380,084
- Issue date Apr 30, 2002
- Chartered Semiconductor Manufacturing Inc.
- Yeow Kheng Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Composite silicon-metal nitride barrier to prevent formation of met...
- Patent number 6,372,636
- Issue date Apr 16, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method for bonding wafers to produce stacked integrated circuits
- Publication number 20050224921
- Publication date Oct 13, 2005
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of copper/copper surface bonding using a conducting polymer...
- Publication number 20050112799
- Publication date May 26, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of copper/copper surface bonding using a conducting polymer...
- Publication number 20050090102
- Publication date Apr 28, 2005
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of copper/copper surface bonding using a conducting polymer...
- Publication number 20050090037
- Publication date Apr 28, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Yakub Aliyu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of copper/copper surface bonding using a conducting polymer...
- Publication number 20050090039
- Publication date Apr 28, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Deposition of barrier metal in damascene interconnects using metal...
- Publication number 20040082169
- Publication date Apr 29, 2004
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of using hydrogen plasma to pre-clean copper surfaces during...
- Publication number 20030192943
- Publication date Oct 16, 2003
- Chartered Semiconductor Manufacturing Ltd.
- John Leonard Sudijono
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Apparatus and methods to clean copper contamination on wafer edge
- Publication number 20030140943
- Publication date Jul 31, 2003
- Chartered Semiconductor Manufacturing Ltd.
- Sudipto Ranendra Roy
- B08 - CLEANING
Information Patent Application
Method of copper/copper surface bonding using a conducting polymer...
- Publication number 20030032275
- Publication date Feb 13, 2003
- Yakub Aliyu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for bonding wafers to produce stacked integrated circuits
- Publication number 20020163072
- Publication date Nov 7, 2002
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to form self-aligned anti-via interconnects
- Publication number 20020155693
- Publication date Oct 24, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Sangki Hong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of extreme ultraviolet mask engineering
- Publication number 20020115000
- Publication date Aug 22, 2002
- Chartered Semiconductor Manufacturing Inc.
- Subhash Gupta
- B82 - NANO-TECHNOLOGY
Information Patent Application
Planarization by selective electro-dissolution
- Publication number 20020115283
- Publication date Aug 22, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Paul Kwok Keung Ho
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Method for stripping copper in damascene interconnects
- Publication number 20020115580
- Publication date Aug 22, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Subhash Gupta
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Method of application of conductive cap-layer in flip-chip, cob, an...
- Publication number 20020100794
- Publication date Aug 1, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Kwok Keung Paul Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for cleaning semiconductor structures using hydrocarbon and...
- Publication number 20020096190
- Publication date Jul 25, 2002
- Chartered Semiconductor Manufacturing Inc.
- Sudipto Ranendra Roy
- C11 - ANIMAL AND VEGETABLE OILS, FATS, FATTY SUBSTANCES AND WAXES FATTY ACIDS...
Information Patent Application
Method to form self-aligned, L-shaped sidewall spacers
- Publication number 20020076877
- Publication date Jun 20, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Subhash Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Composite silicon-metal nitride barrier to prevent formation of met...
- Publication number 20020064941
- Publication date May 30, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Application of vapor phase HFACAC-based compound for use in copper...
- Publication number 20020048950
- Publication date Apr 25, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Yakub Aliyu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Non metallic barrier formations for copper damascene type interconn...
- Publication number 20020001952
- Publication date Jan 3, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non metallic barrier formations for copper damascene type interconn...
- Publication number 20020001951
- Publication date Jan 3, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-conductive barrier formations for copper damascene type interco...
- Publication number 20010055878
- Publication date Dec 27, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-metallic barrier formations for copper damascene type interconn...
- Publication number 20010049195
- Publication date Dec 6, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to deposit a copper layer
- Publication number 20010029099
- Publication date Oct 11, 2001
- Chartered Semiconductor Manufacturing Ltd.
- Paul Kwok Keung Ho
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Subhash Gupta

Person

Patents Grantslast 30 patents

Method of copper/copper surface bonding using a conducting polymer...

Method of copper/copper surface bonding using a conducting polymer...

Method of copper/copper surface bonding using a conducting polymer...

Method of copper/copper surface bonding using a conducting polymer...

Apparatus and methods to clean copper contamination on wafer edge

Method to form copper interconnects by adding an aluminum layer to...

Method of using hydrogen plasma to pre-clean copper surfaces during...

Method of application of conductive cap-layer in flip-chip, cob, an...

Method for cleaning semiconductor structures using hydrocarbon and...

Method to create a copper diffusion deterrent interface

Method of extreme ultraviolet mask engineering

Method for stripping copper in damascene interconnects

Non-metallic barrier formations for copper damascene type interconn...

Method and apparatus for removing contaminants from the perimeter o...

Non-metallic barrier formations for copper damascene type interconn...

Non-metallic barrier formations for copper damascene type interconn...

Method of manufacturing embedded organic stop layer for dual damasc...

Dual layer pattern formation method for dual damascene interconnect

Composite silicon-metal nitride barrier to prevent formation of met...

Method to create copper traps by modifying treatment on the dielect...

Non metallic barrier formations for copper damascene type interconn...

Method of application of displacement reaction to form a conductive...

Method of application of copper solution in flip-chip, COB, and mic...

Method for stripping copper in damascene interconnects

Method to thin down copper barriers in deep submicron geometries by...

Method to form self-aligned, L-shaped sidewall spacers

CMP process utilizing dummy plugs in damascene process

Method of application of conductive cap-layer in flip-chip, COB, an...

Method to form high performance copper damascene interconnects by d...

Composite silicon-metal nitride barrier to prevent formation of met...

Patents Applicationslast 30 patents

Method for bonding wafers to produce stacked integrated circuits

Method of copper/copper surface bonding using a conducting polymer...

Method of copper/copper surface bonding using a conducting polymer...

Method of copper/copper surface bonding using a conducting polymer...

Method of copper/copper surface bonding using a conducting polymer...

Deposition of barrier metal in damascene interconnects using metal...

Method of using hydrogen plasma to pre-clean copper surfaces during...

Apparatus and methods to clean copper contamination on wafer edge

Method of copper/copper surface bonding using a conducting polymer...

Method for bonding wafers to produce stacked integrated circuits

Method to form self-aligned anti-via interconnects

Method of extreme ultraviolet mask engineering

Planarization by selective electro-dissolution

Method for stripping copper in damascene interconnects

Method of application of conductive cap-layer in flip-chip, cob, an...

Method for cleaning semiconductor structures using hydrocarbon and...

Method to form self-aligned, L-shaped sidewall spacers

Composite silicon-metal nitride barrier to prevent formation of met...

Application of vapor phase HFACAC-based compound for use in copper...

Non metallic barrier formations for copper damascene type interconn...

Non metallic barrier formations for copper damascene type interconn...

Non-conductive barrier formations for copper damascene type interco...

Non-metallic barrier formations for copper damascene type interconn...

Method to deposit a copper layer