Subhasish Mitra

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit and method for programming resistive memory cells
- Patent number 11,217,307
- Issue date Jan 4, 2022
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Elisa Vianello
- G11 - INFORMATION STORAGE
Information Patent Grant
System-level validation of systems-on-a-chip (SoC)
- Patent number 10,546,079
- Issue date Jan 28, 2020
- The Board of Trustees of the Leland Stanford Junior University
- Subhasish Mitra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-silicon validation and debug using symbolic quick error detection
- Patent number 10,528,448
- Issue date Jan 7, 2020
- The Board of Trustees of the Leland Stanford Junior University
- Subhasish Mitra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for detecting bugs in logic-based processing devices
- Patent number 10,120,737
- Issue date Nov 6, 2018
- The Board of Trustees of the Leland Stanford Junior University
- Hai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for testing a logic-based processing device
- Patent number 9,928,150
- Issue date Mar 27, 2018
- The Board of Trustees of the Leland Stanford Junior University
- Hai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Word voter for redundant systems
- Patent number 6,910,173
- Issue date Jun 21, 2005
- The Board of Trustees of the Leland Stanford Junior University
- Subhasish Mitra
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
GENERALIZED QED PRE-SILICON VERIFICATION FRAMEWORK
- Publication number 20250200258
- Publication date Jun 19, 2025
- The Board of Trustees of the Leland Stanford Junior University
- Subhasish Mitra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT AND METHOD FOR PROGRAMMING RESISTIVE MEMORY CELLS
- Publication number 20210035638
- Publication date Feb 4, 2021
- Commissariat a I'Energie Atomique et aux Energies Alternatives
- Elisa VIANELLO
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM-LEVEL VALIDATION OF SYSTEMS-ON-A-CHIP (SoC)
- Publication number 20180165393
- Publication date Jun 14, 2018
- The Board of Trustees of the Leland Stanford Junior University
- Subhasish MITRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-SILICON VALIDATION AND DEBUG USING SYMBOLIC QUICK ERROR DETECTION
- Publication number 20180157574
- Publication date Jun 7, 2018
- The Board of Trustees of the Leland Stanford Junior University
- Subhasish MITRA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR DETECTING BUGS IN LOGIC-BASED PROCESSING DEVICES
- Publication number 20160245865
- Publication date Aug 25, 2016
- The Board of Trustees of the Leland Stanford Junior University
- Hai Lin
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR TESTING A LOGIC-BASED PROCESSING DEVICE
- Publication number 20150377961
- Publication date Dec 31, 2015
- The Board of Trustees of the Leland Stanford Junior University
- Hai Lin
- G01 - MEASURING TESTING
Information Patent Application
Reliability degradation compensation using body bias
- Publication number 20070164371
- Publication date Jul 19, 2007
- James W. Tschanz
- G01 - MEASURING TESTING
Information Patent Application
Error-detection flip-flop
- Publication number 20070168848
- Publication date Jul 19, 2007
- James Tschanz
- G01 - MEASURING TESTING
Information Patent Application
Word voter for redundant systems
- Publication number 20020116683
- Publication date Aug 22, 2002
- Subhasish Mitra
- G06 - COMPUTING CALCULATING COUNTING

Subhasish Mitra

Person

Patents Grantslast 30 patents

Circuit and method for programming resistive memory cells

System-level validation of systems-on-a-chip (SoC)

Post-silicon validation and debug using symbolic quick error detection

Apparatus for detecting bugs in logic-based processing devices

System and method for testing a logic-based processing device

Word voter for redundant systems

Patents Applicationslast 30 patents

GENERALIZED QED PRE-SILICON VERIFICATION FRAMEWORK

CIRCUIT AND METHOD FOR PROGRAMMING RESISTIVE MEMORY CELLS

SYSTEM-LEVEL VALIDATION OF SYSTEMS-ON-A-CHIP (SoC)

POST-SILICON VALIDATION AND DEBUG USING SYMBOLIC QUICK ERROR DETECTION

APPARATUS FOR DETECTING BUGS IN LOGIC-BASED PROCESSING DEVICES

SYSTEM AND METHOD FOR TESTING A LOGIC-BASED PROCESSING DEVICE

Reliability degradation compensation using body bias

Error-detection flip-flop

Word voter for redundant systems