Subhasish Mitra

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compacting circuit responses
- Patent number 7,814,383
- Issue date Oct 12, 2010
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Grant
Compacting circuit responses
- Patent number 7,574,640
- Issue date Aug 11, 2009
- Intel Corporation
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Grant
System and shadow bistable circuits coupled to output joining circuit
- Patent number 7,523,371
- Issue date Apr 21, 2009
- Intel Corporation
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Grant
Error-detection flip-flop
- Patent number 7,409,631
- Issue date Aug 5, 2008
- Intel Corporation
- James Tschanz
- G01 - MEASURING TESTING
Information Patent Grant
System pulse latch and shadow pulse latch coupled to output joining...
- Patent number 7,373,572
- Issue date May 13, 2008
- Intel Corporation
- Tak M. Mak
- G01 - MEASURING TESTING
Information Patent Grant
System and shadow circuits with output joining circuit
- Patent number 7,278,074
- Issue date Oct 2, 2007
- Intel Corporation
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Grant
System and scanout circuits with error resilience circuit
- Patent number 7,278,076
- Issue date Oct 2, 2007
- Intel Corporation
- Ming Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Stimulus generation
- Patent number 7,240,260
- Issue date Jul 3, 2007
- Intel Corporation
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Grant
Error detecting circuit
- Patent number 7,188,284
- Issue date Mar 6, 2007
- Intel Corporation
- Subhasish Mitra
- G11 - INFORMATION STORAGE
Information Patent Grant
Compacting circuit responses
- Patent number 7,185,253
- Issue date Feb 27, 2007
- Intel Corporation
- Subhasish Mitra
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
System and shadow circuits with output joining circuit
- Publication number 20060168489
- Publication date Jul 27, 2006
- Intel Corporation
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Application
System pulse latch and shadow pulse latch coupled to output joining...
- Publication number 20060168487
- Publication date Jul 27, 2006
- Intel Corporation
- Tak M. Mak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Localizing error detection and recovery
- Publication number 20060143551
- Publication date Jun 29, 2006
- Intel Corporation
- Arijit Biswas
- G01 - MEASURING TESTING
Information Patent Application
Compacting circuit responses
- Publication number 20060036985
- Publication date Feb 16, 2006
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Application
System and shadow bistable circuits coupled to output joining circuit
- Publication number 20060015786
- Publication date Jan 19, 2006
- Intel Corporation
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Application
Error detecting circuit
- Publication number 20060005091
- Publication date Jan 5, 2006
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Application
System and scanout circuits with error resilience circuit
- Publication number 20060005103
- Publication date Jan 5, 2006
- Intel Corporation
- Ming Zhang
- G01 - MEASURING TESTING
Information Patent Application
Compacting circuit responses
- Publication number 20050055613
- Publication date Mar 10, 2005
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Application
Stimulus generation
- Publication number 20040117703
- Publication date Jun 17, 2004
- Subhasish Mitra
- G01 - MEASURING TESTING
Information Patent Application
Compacting circuit responses
- Publication number 20030188269
- Publication date Oct 2, 2003
- Subhasish Mitra
- G01 - MEASURING TESTING

Subhasish Mitra

Person

Patents Grantslast 30 patents

Compacting circuit responses

Compacting circuit responses

System and shadow bistable circuits coupled to output joining circuit

Error-detection flip-flop

System pulse latch and shadow pulse latch coupled to output joining...

System and shadow circuits with output joining circuit

System and scanout circuits with error resilience circuit

Stimulus generation

Error detecting circuit

Compacting circuit responses

Patents Applicationslast 30 patents

System and shadow circuits with output joining circuit

System pulse latch and shadow pulse latch coupled to output joining...

Localizing error detection and recovery

Compacting circuit responses

System and shadow bistable circuits coupled to output joining circuit

Error detecting circuit

System and scanout circuits with error resilience circuit

Compacting circuit responses

Stimulus generation

Compacting circuit responses