Subhrajit Bhattacharya

Person

White Plains, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
System for using partitioned masks to build a chip
- Patent number 7,870,531
- Issue date Jan 11, 2011
- International Business Machines Corporation
- Subhrajit Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modeling and simulating a powergated hierarchical element
- Patent number 7,516,424
- Issue date Apr 7, 2009
- International Business Machines Corporation
- Stephen J. Barnfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Influence-based circuit design
- Patent number 7,500,207
- Issue date Mar 3, 2009
- International Business Machines Corporation
- Subhrajit Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power gating techniques able to have data retention and variability...
- Patent number 7,479,801
- Issue date Jan 20, 2009
- International Business Machines Corporation
- Subhrajit Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for using partitioned masks to build a chip
- Patent number 7,469,401
- Issue date Dec 23, 2008
- International Business Machines Corporation
- Subhrajit Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power gating techniques able to have data retention and variability...
- Patent number 7,420,388
- Issue date Sep 2, 2008
- International Business Machines Corp.
- Subhrajit Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power gating techniques able to have data retention and variability...
- Patent number 7,126,370
- Issue date Oct 24, 2006
- International Business Machines Corporation
- Subhrajit Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and arrangements for automatically interconnecting cores in...
- Patent number 6,993,740
- Issue date Jan 31, 2006
- International Business Machines Corporation
- Reinaldo A. Bergamaschi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and arrangements for automatic synthesis of systems-on-chip
- Patent number 6,477,691
- Issue date Nov 5, 2002
- International Business Machines Corporation
- Reinaldo A. Bergamashi/Rab
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM FOR USING PARTITIONED MASKS TO BUILD A CHIP
- Publication number 20080216037
- Publication date Sep 4, 2008
- Subhrajit Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Power Gating Techniques Able to Have Data Retention And Variability...
- Publication number 20080143431
- Publication date Jun 19, 2008
- Subhrajit Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Modeling and simulating a powergated hierarchical element
- Publication number 20070198237
- Publication date Aug 23, 2007
- International Business Machines Corporation
- Stephen J. Barnfield
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for using partitioned masks to build a chip
- Publication number 20070196958
- Publication date Aug 23, 2007
- International Business Machines Corporation
- Subhrajit Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Influence-based circuit design
- Publication number 20070192752
- Publication date Aug 16, 2007
- International Business Machines Corporation
- Subhrajit Bhattacharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power gating techniques able to have data retention and variability...
- Publication number 20060267629
- Publication date Nov 30, 2006
- Subhrajit Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Power gating techniques able to have data retention and variability...
- Publication number 20060091913
- Publication date May 4, 2006
- International Business Machines Corporation
- Subhrajit Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY

Subhrajit Bhattacharya

Person

Patents Grantslast 30 patents

System for using partitioned masks to build a chip

Modeling and simulating a powergated hierarchical element

Influence-based circuit design

Power gating techniques able to have data retention and variability...

Method for using partitioned masks to build a chip

Power gating techniques able to have data retention and variability...

Power gating techniques able to have data retention and variability...

Methods and arrangements for automatically interconnecting cores in...

Methods and arrangements for automatic synthesis of systems-on-chip

Patents Applicationslast 30 patents

SYSTEM FOR USING PARTITIONED MASKS TO BUILD A CHIP

Power Gating Techniques Able to Have Data Retention And Variability...

Modeling and simulating a powergated hierarchical element

Method for using partitioned masks to build a chip

Influence-based circuit design

Power gating techniques able to have data retention and variability...

Power gating techniques able to have data retention and variability...