Subramanian S Iyer

Person

Los Angeles, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
On-chip electrostatic discharge sensor
- Patent number 12,148,748
- Issue date Nov 19, 2024
- The Regents of the University of California
- Subramanian Iyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flexible spinal cord stimulators for pain and trauma management thr...
- Patent number 11,992,686
- Issue date May 28, 2024
- The Regents of the University of California
- Bilwaj Gaonkar
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
Flexible and stretchable interconnects for flexible systems
- Patent number 11,538,764
- Issue date Dec 27, 2022
- The Regents of the University of California
- Subramanian S. Iyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power distribution within silicon interconnect fabric
- Patent number 11,257,746
- Issue date Feb 22, 2022
- The Regents of the University of California
- Boris Vaisband
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Network on interconnect fabric and integrated antenna
- Patent number 11,239,542
- Issue date Feb 1, 2022
- The Regents of the University of California
- Boris Vaisband
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Authenticating a hardware chip using an intrinsic chip identifier
- Patent number 11,210,373
- Issue date Dec 28, 2021
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible fan-out wafer level process and structure
- Patent number 10,930,601
- Issue date Feb 23, 2021
- The Regents of the University of California
- Subramanian S. Iyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect circuits at three-dimensional (3-D) bonding interfaces...
- Patent number 10,740,282
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing an authenticating service of a chip
- Patent number 10,657,231
- Issue date May 19, 2020
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and implementation of cortical system, and fabricating...
- Patent number 10,613,754
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fine-grained analog memory device based on charge-trapping in high-...
- Patent number 10,585,643
- Issue date Mar 10, 2020
- The Regents of the University of California
- Xuefeng Gu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and implementation of cortical system, and fabricating...
- Patent number 10,503,402
- Issue date Dec 10, 2019
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thermally enhanced package to reduce thermal interaction between dies
- Patent number 10,461,067
- Issue date Oct 29, 2019
- GLOBALFOUNDRIES Inc.
- Janak Patel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Providing an authenticating service of a chip
- Patent number 10,262,119
- Issue date Apr 16, 2019
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Faulty core recovery mechanisms for a three-dimensional network on...
- Patent number 10,176,063
- Issue date Jan 8, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect circuits at three dimensional (3-D) bonding interfaces...
- Patent number 9,940,302
- Issue date Apr 10, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and implementation of cortical system, and fabricating...
- Patent number 9,886,193
- Issue date Feb 6, 2018
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thermally enhanced package to reduce thermal interaction between dies
- Patent number 9,859,262
- Issue date Jan 2, 2018
- GLOBALFOUNDRIES Inc.
- Janak Patel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Array of processor core circuits with reversible tiers
- Patent number 9,792,251
- Issue date Oct 17, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for forming through silicon via in N+ epitaxy wafers with re...
- Patent number 9,748,114
- Issue date Aug 29, 2017
- International Business Machines Corporation
- Kangguo Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Providing an authenticating service of a chip
- Patent number 9,690,927
- Issue date Jun 27, 2017
- International Business Machines Corporation
- Srivatsan Chellappa
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Array of processor core circuits with reversible tiers
- Patent number 9,588,937
- Issue date Mar 7, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combination of TSV and back side wiring in 3D integration
- Patent number 9,543,229
- Issue date Jan 10, 2017
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Combination of TSV and back side wiring in 3D integration
- Patent number 9,536,809
- Issue date Jan 3, 2017
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to achieve ultra-high chip-to-chip alignment accuracy for wa...
- Patent number 9,466,538
- Issue date Oct 11, 2016
- GLOBALFOUNDRIES Inc.
- Spyridon Skordas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Physically unclonable fuse using a NOR type memory array
- Patent number 9,436,845
- Issue date Sep 6, 2016
- GLOBALFOUNDRIES Inc.
- Subramanian S. Iyer
- G11 - INFORMATION STORAGE
Information Patent Grant
Wiring structure for trench fuse component with methods of fabrication
- Patent number 9,431,339
- Issue date Aug 30, 2016
- International Business Machines Corporation
- Toshiaki Kirihata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wiring structure for trench fuse component with methods of fabrication
- Patent number 9,431,340
- Issue date Aug 30, 2016
- International Business Machines Corporation
- Toshiaki Kirihata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional integrated circuit integration using dielectric b...
- Patent number 9,406,561
- Issue date Aug 2, 2016
- International Business Machines Corporation
- Mukta G. Farooq
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect circuits at three-dimensional (3-D) bonding interfaces...
- Patent number 9,368,489
- Issue date Jun 14, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NONVOLATIVE MEMORY DEVICES WITH CHARGE TRAP TRANSISTOR STRUCTURES A...
- Publication number 20240087647
- Publication date Mar 14, 2024
- The Regents of the University of California
- Sepideh NOURI
- G11 - INFORMATION STORAGE
Information Patent Application
NEURAL NETWORK SYSTEM WITH NEURONS INCLUDING CHARGE-TRAP TRANSISTOR...
- Publication number 20240028884
- Publication date Jan 25, 2024
- The Regents of the University of California
- Steven L. MORAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE INORGANIC MICROLED DISPLAY DEVICE AND METHOD OF MANUFACTUR...
- Publication number 20230238476
- Publication date Jul 27, 2023
- The Regents of the University of California
- Subramanian S. IYER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR SUPERCONDUCTING SILICON INTERCONNECT SUBSTRAT...
- Publication number 20230225225
- Publication date Jul 13, 2023
- The Regents of the University of California
- Yu-Tao YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR CHANGING THE FUNCTIONALITY OF AN INTEGRATE...
- Publication number 20230178146
- Publication date Jun 8, 2023
- The Regents of the University of California
- Sepideh NOURI
- G11 - INFORMATION STORAGE
Information Patent Application
ON-CHIP ELECTROSTATIC DISCHARGE SENSOR
- Publication number 20220392893
- Publication date Dec 8, 2022
- The Regents of the University of California
- Subramanian IYER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER DISTRIBUTION WITHIN SILICON INTERCONNECT FABRIC
- Publication number 20210225749
- Publication date Jul 22, 2021
- The Regents of the University of California
- Boris Vaisband
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLEXIBLE AND STRETCHABLE INTERCONNECTS FOR FLEXIBLE SYSTEMS
- Publication number 20210074648
- Publication date Mar 11, 2021
- The Regents of the University of California
- Subramanian S. IYER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLEXIBLE SPINAL CORD STIMULATORS FOR PAIN AND TRAUMA MANAGEMENT THR...
- Publication number 20200406039
- Publication date Dec 31, 2020
- The Regents of the University of California
- Bilwaj Gaonkar
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
NETWORK ON INTERCONNECT FABRIC AND INTEGRATED ANTENNA
- Publication number 20200403293
- Publication date Dec 24, 2020
- The Regents of the University of California
- Boris Vaisband
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-AUTHENTICATING CHIP
- Publication number 20200074051
- Publication date Mar 5, 2020
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...
- Publication number 20200042182
- Publication date Feb 6, 2020
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES
- Publication number 20190378829
- Publication date Dec 12, 2019
- GLOBALFOUNDRIES INC.
- Janak PATEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLEXIBLE FAN-OUT WAFER LEVEL PROCESS AND STRUCTURE
- Publication number 20190287927
- Publication date Sep 19, 2019
- The Regents of the University of California
- Subramanian S. IYER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-AUTHENTICATING CHIP
- Publication number 20190155999
- Publication date May 23, 2019
- International Business Machines Corporation
- Srivatsan Chellappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...
- Publication number 20180189233
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...
- Publication number 20180136846
- Publication date May 17, 2018
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES
- Publication number 20180068993
- Publication date Mar 8, 2018
- GLOBALFOUNDRIES Inc.
- Janak PATEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES
- Publication number 20180012878
- Publication date Jan 11, 2018
- GLOBALFOUNDRIES INC.
- Janak PATEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINE-GRAINED ANALOG MEMORY DEVICE BASED ON CHARGE-TRAPPING IN HIGH-...
- Publication number 20170329575
- Publication date Nov 16, 2017
- The Regents of the University of California
- Xuefeng Gu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-AUTHENTICATING CHIP
- Publication number 20170220784
- Publication date Aug 3, 2017
- International Business Machines Corporation
- Srivatsan Chellappa
- G01 - MEASURING TESTING
Information Patent Application
ARRAY OF PROCESSOR CORE CIRCUITS WITH REVERSIBLE TIERS
- Publication number 20170124024
- Publication date May 4, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...
- Publication number 20160334991
- Publication date Nov 17, 2016
- International Business Machines Corporation
- Daniel G. Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...
- Publication number 20160239393
- Publication date Aug 18, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT CIRCUITS AT THREE DIMENSIONAL (3-D) BONDING INTERFACES...
- Publication number 20160232128
- Publication date Aug 11, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WIRING STRUCTURE FOR TRENCH FUSE COMPONENT WITH METHODS OF FABRICATION
- Publication number 20160163642
- Publication date Jun 9, 2016
- International Business Machines Corporation
- Toshiaki Kirihata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...
- Publication number 20160154717
- Publication date Jun 2, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...
- Publication number 20160148901
- Publication date May 26, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION
- Publication number 20150371927
- Publication date Dec 24, 2015
- International Business Machines Corporation
- Pooja R. Batra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-VOLATILE MEMORY BASED ON RETENTION MODULATION
- Publication number 20150279462
- Publication date Oct 1, 2015
- International Business Machines Corporation
- Subramanian S. Iyer
- G11 - INFORMATION STORAGE

Subramanian S Iyer

Person

Patents Grantslast 30 patents

On-chip electrostatic discharge sensor

Flexible spinal cord stimulators for pain and trauma management thr...

Flexible and stretchable interconnects for flexible systems

Power distribution within silicon interconnect fabric

Network on interconnect fabric and integrated antenna

Authenticating a hardware chip using an intrinsic chip identifier

Flexible fan-out wafer level process and structure

Interconnect circuits at three-dimensional (3-D) bonding interfaces...

Providing an authenticating service of a chip

Architecture and implementation of cortical system, and fabricating...

Fine-grained analog memory device based on charge-trapping in high-...

Architecture and implementation of cortical system, and fabricating...

Thermally enhanced package to reduce thermal interaction between dies

Providing an authenticating service of a chip

Faulty core recovery mechanisms for a three-dimensional network on...

Interconnect circuits at three dimensional (3-D) bonding interfaces...

Architecture and implementation of cortical system, and fabricating...

Thermally enhanced package to reduce thermal interaction between dies

Array of processor core circuits with reversible tiers

Method for forming through silicon via in N+ epitaxy wafers with re...

Providing an authenticating service of a chip

Array of processor core circuits with reversible tiers

Combination of TSV and back side wiring in 3D integration

Combination of TSV and back side wiring in 3D integration

Method to achieve ultra-high chip-to-chip alignment accuracy for wa...

Physically unclonable fuse using a NOR type memory array

Wiring structure for trench fuse component with methods of fabrication

Wiring structure for trench fuse component with methods of fabrication

Three dimensional integrated circuit integration using dielectric b...

Interconnect circuits at three-dimensional (3-D) bonding interfaces...

Patents Applicationslast 30 patents

NONVOLATIVE MEMORY DEVICES WITH CHARGE TRAP TRANSISTOR STRUCTURES A...

NEURAL NETWORK SYSTEM WITH NEURONS INCLUDING CHARGE-TRAP TRANSISTOR...

FLEXIBLE INORGANIC MICROLED DISPLAY DEVICE AND METHOD OF MANUFACTUR...

SYSTEM AND METHOD FOR SUPERCONDUCTING SILICON INTERCONNECT SUBSTRAT...

APPARATUS AND METHOD FOR CHANGING THE FUNCTIONALITY OF AN INTEGRATE...

ON-CHIP ELECTROSTATIC DISCHARGE SENSOR

POWER DISTRIBUTION WITHIN SILICON INTERCONNECT FABRIC

FLEXIBLE AND STRETCHABLE INTERCONNECTS FOR FLEXIBLE SYSTEMS

FLEXIBLE SPINAL CORD STIMULATORS FOR PAIN AND TRAUMA MANAGEMENT THR...

NETWORK ON INTERCONNECT FABRIC AND INTEGRATED ANTENNA

SELF-AUTHENTICATING CHIP

ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...

THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES

FLEXIBLE FAN-OUT WAFER LEVEL PROCESS AND STRUCTURE

SELF-AUTHENTICATING CHIP

INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...

ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...

THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES

THERMALLY ENHANCED PACKAGE TO REDUCE THERMAL INTERACTION BETWEEN DIES

FINE-GRAINED ANALOG MEMORY DEVICE BASED ON CHARGE-TRAPPING IN HIGH-...

SELF-AUTHENTICATING CHIP

ARRAY OF PROCESSOR CORE CIRCUITS WITH REVERSIBLE TIERS

ARCHITECTURE AND IMPLEMENTATION OF CORTICAL SYSTEM, AND FABRICATING...

FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...

INTERCONNECT CIRCUITS AT THREE DIMENSIONAL (3-D) BONDING INTERFACES...

WIRING STRUCTURE FOR TRENCH FUSE COMPONENT WITH METHODS OF FABRICATION

FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...

INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...

COMBINATION OF TSV AND BACK SIDE WIRING IN 3D INTEGRATION

NON-VOLATILE MEMORY BASED ON RETENTION MODULATION