Subramanyam Sripada

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Look-ahead timing prediction for multi-instance module (MIM) engine...
- Patent number 10,339,258
- Issue date Jul 2, 2019
- Synopsys, Inc.
- Seungwhun Paik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simplifying modes of an electronic circuit by reducing constraints
- Patent number 9,489,478
- Issue date Nov 8, 2016
- Synopsys, Inc.
- Ajit Sequeira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining a design attribute by estimation and by calibration of...
- Patent number 8,924,906
- Issue date Dec 30, 2014
- Synopsys, Inc.
- Nahmsuk Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic reduction of modes of electronic circuits for timing anal...
- Patent number 8,701,074
- Issue date Apr 15, 2014
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of merged mode constraints for electronic circ...
- Patent number 8,627,262
- Issue date Jan 7, 2014
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic verification of merged mode constraints for electronic ci...
- Patent number 8,607,186
- Issue date Dec 10, 2013
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining a design attribute by estimation and by calibration of...
- Patent number 8,555,235
- Issue date Oct 8, 2013
- Synopsys, Inc.
- Nahmsuk Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel parasitic processing in static timing analysis
- Patent number 8,473,886
- Issue date Jun 25, 2013
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining a design attribute by estimation and by calibration of...
- Patent number 7,900,165
- Issue date Mar 1, 2011
- Synopsys, Inc.
- Nahmsuk Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for providing distributed static timing analysis...
- Patent number 7,739,098
- Issue date Jun 15, 2010
- Synopsys, Inc.
- Kayhan Küçükçakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical signal integrity analysis using interface logic models
- Patent number 7,523,428
- Issue date Apr 21, 2009
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical signal integrity analysis using interface logic models
- Patent number 7,216,317
- Issue date May 8, 2007
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STATIC TIMING ANALYSIS OF MULTI-DIE THREE-DIMENSIONAL INTEGRATED CI...
- Publication number 20230306180
- Publication date Sep 28, 2023
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOK-AHEAD TIMING PREDICTION FOR MULTI-INSTANCE MODULE (MIM) ENGINE...
- Publication number 20170004244
- Publication date Jan 5, 2017
- Synopsys, Inc.
- Seungwhun Paik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Simplifying Modes of an Electronic Circuit by Reducing Constraints
- Publication number 20160110485
- Publication date Apr 21, 2016
- Synopsys, Inc.
- Ajit Sequeira
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Determining A Design Attribute By Estimation And By Calibration Of...
- Publication number 20140059508
- Publication date Feb 27, 2014
- Synopsys, Inc.
- Nahmsuk Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC REDUCTION OF MODES OF ELECTRONIC CIRCUITS FOR TIMING ANAL...
- Publication number 20120324410
- Publication date Dec 20, 2012
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel Parasitic Processing In Static Timing Analysis
- Publication number 20120066656
- Publication date Mar 15, 2012
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRC...
- Publication number 20110252393
- Publication date Oct 13, 2011
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CI...
- Publication number 20110252390
- Publication date Oct 13, 2011
- Synopsys, Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING A DESIGN ATTRIBUTE BY ESTIMATION AND BY CALIBRATION OF...
- Publication number 20110113396
- Publication date May 12, 2011
- Nahmsuk Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Determining a design attribute by estimation and by calibration of...
- Publication number 20080243414
- Publication date Oct 2, 2008
- Synopsys, Inc.
- Nahmsuk Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchical Signal Integrity Analysis Using Interface Logic Models
- Publication number 20070168897
- Publication date Jul 19, 2007
- Synopsys Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchical signal integrity analysis using interface logic models
- Publication number 20050229128
- Publication date Oct 13, 2005
- Synopsys Inc.
- Subramanyam Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for providing distributed static timing analysis...
- Publication number 20050172250
- Publication date Aug 4, 2005
- Synopsys, Inc.
- Kayhan Kucukcakar
- G06 - COMPUTING CALCULATING COUNTING

Subramanyam Sripada

Person

Patents Grantslast 30 patents

Look-ahead timing prediction for multi-instance module (MIM) engine...

Simplifying modes of an electronic circuit by reducing constraints

Determining a design attribute by estimation and by calibration of...

Automatic reduction of modes of electronic circuits for timing anal...

Automatic generation of merged mode constraints for electronic circ...

Automatic verification of merged mode constraints for electronic ci...

Determining a design attribute by estimation and by calibration of...

Parallel parasitic processing in static timing analysis

Determining a design attribute by estimation and by calibration of...

System and method for providing distributed static timing analysis...

Hierarchical signal integrity analysis using interface logic models

Hierarchical signal integrity analysis using interface logic models

Patents Applicationslast 30 patents

STATIC TIMING ANALYSIS OF MULTI-DIE THREE-DIMENSIONAL INTEGRATED CI...

LOOK-AHEAD TIMING PREDICTION FOR MULTI-INSTANCE MODULE (MIM) ENGINE...

Simplifying Modes of an Electronic Circuit by Reducing Constraints

Determining A Design Attribute By Estimation And By Calibration Of...

AUTOMATIC REDUCTION OF MODES OF ELECTRONIC CIRCUITS FOR TIMING ANAL...

Parallel Parasitic Processing In Static Timing Analysis

AUTOMATIC GENERATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CIRC...

AUTOMATIC VERIFICATION OF MERGED MODE CONSTRAINTS FOR ELECTRONIC CI...

DETERMINING A DESIGN ATTRIBUTE BY ESTIMATION AND BY CALIBRATION OF...

Determining a design attribute by estimation and by calibration of...

Hierarchical Signal Integrity Analysis Using Interface Logic Models

Hierarchical signal integrity analysis using interface logic models

System and method for providing distributed static timing analysis...