Sudeep Mondal

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New Delhi, IN

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Patents Grantslast 30 patents

Information Patent Grant
Verifying glitches in reset path using formal verification and simu...
- Patent number 11,238,202
- Issue date Feb 1, 2022
- Synopsys, Inc.
- Sudeep Mondal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock domain crossing verification of integrated circuit design usi...
- Patent number 11,087,059
- Issue date Aug 10, 2021
- Synopsys, Inc.
- Anshu Malani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for managing and composing verification engines
- Patent number 10,387,605
- Issue date Aug 20, 2019
- Synopsys, Inc.
- Maher Mneimneh
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
VERIFYING GLITCHES IN RESET PATH USING FORMAL VERIFICATION AND SIMU...
- Publication number 20200401750
- Publication date Dec 24, 2020
- Synopsys, Inc.
- Sudeep MONDAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL ABSTRACTION FLOW USING PARAMETER INFERENCE
- Publication number 20200401749
- Publication date Dec 24, 2020
- Synopsys, Inc.
- Anshu MALANI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MANAGING AND COMPOSING VERIFICATION ENGINES
- Publication number 20170024508
- Publication date Jan 26, 2017
- Synopsys, Inc.
- Maher Mneimneh
- G06 - COMPUTING CALCULATING COUNTING