Sudhakar Surendran

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Techniques for modeling and verification of convergence for hierarc...
- Patent number 12,197,840
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to simulate metastability for circuit design...
- Patent number 11,775,718
- Issue date Oct 3, 2023
- Texas Instruments Incorporated
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for comprehensive integration verification of mixed-signal c...
- Patent number 11,669,668
- Issue date Jun 6, 2023
- Texas Instruments Incorporated
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to simulate metastability for circuit design...
- Patent number 11,531,798
- Issue date Dec 20, 2022
- Texas Instmments Incorporated
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for comprehensive integration verification of mixed-signal c...
- Patent number 11,334,701
- Issue date May 17, 2022
- Texas Instruments Incorporated
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for comprehensive integration verification of mixed-signal c...
- Patent number 10,949,594
- Issue date Mar 16, 2021
- Texas Instruments Incorporated
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for comprehensive integration verification of mixed-signal c...
- Patent number 10,489,538
- Issue date Nov 26, 2019
- Texas Instruments Incorporated
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch termination at powered down memory bank boundary in shared...
- Patent number 8,117,398
- Issue date Feb 14, 2012
- Texas Instruments Incorporated
- Sajish Sajayan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Multiprocessor system power management of shared memories powering...
- Patent number 8,112,652
- Issue date Feb 7, 2012
- Texas Instruments Incorporated
- Sajish Sajayan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Power management in federated/distributed shared memory architecture
- Patent number 8,078,897
- Issue date Dec 13, 2011
- Texas Instruments Incorporated
- Sajish Sajayan
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
MANAGING CLOCK TRIGGER SIGNALS FOR ASYNCHRONOUS CLOCK DOMAINS
- Publication number 20240310868
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Gregory North
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONTROL OF A MULTI-TRIM OSCILLATOR
- Publication number 20240313749
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Gregory North
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRACKING COVERAGE ARTIFACTS FOR PERIODIC SIGNALS USING SEQUENCE-BAS...
- Publication number 20240193337
- Publication date Jun 13, 2024
- INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR
- Ayan Chakraborty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL CDC AND RDC VERIFICATION
- Publication number 20230244841
- Publication date Aug 3, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MODELING AND VERIFICATION OF CONVERGENCE FOR HIERARC...
- Publication number 20230205969
- Publication date Jun 29, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar SURENDRAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFYING GLITCHES AND LEVELS IN MIXED-SIGNAL WAVEFORMS
- Publication number 20230176100
- Publication date Jun 8, 2023
- INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR
- Sayandeep Sanyal
- G01 - MEASURING TESTING
Information Patent Application
TECHNIQUES FOR DESIGN VERIFICATION OF DOMAIN CROSSINGS
- Publication number 20230110701
- Publication date Apr 13, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar SURENDRAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO SIMULATE METASTABILITY FOR CIRCUIT DESIGN...
- Publication number 20230088503
- Publication date Mar 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO SIMULATE METASTABILITY FOR CIRCUIT DESIGN...
- Publication number 20220269845
- Publication date Aug 25, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR COMPREHENSIVE INTEGRATION VERIFICATION OF MIXED-SIGNAL C...
- Publication number 20220237355
- Publication date Jul 28, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR COMPREHENSIVE INTEGRATION VERIFICATION OF MIXED-SIGNAL C...
- Publication number 20210157967
- Publication date May 27, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR COMPREHENSIVE INTEGRATION VERIFICATION OF MIXED-SIGNAL C...
- Publication number 20200050724
- Publication date Feb 13, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR COMPREHENSIVE INTEGRATION VERIFICATION OF MIXED-SIGNAL C...
- Publication number 20170124239
- Publication date May 4, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Sudhakar Surendran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware Controlled Power Management of Shared Memories
- Publication number 20090249105
- Publication date Oct 1, 2009
- Sajish Sajayan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Power Management in Federated/Distributed Shared Memory Architecture
- Publication number 20090193270
- Publication date Jul 30, 2009
- Sajish Sajayan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prefetch Termination at Powered Down Memory Bank Boundary in Shared...
- Publication number 20090187715
- Publication date Jul 23, 2009
- Sajish Sajayan
- G06 - COMPUTING CALCULATING COUNTING

Sudhakar Surendran

Person

Patents Grantslast 30 patents

Techniques for modeling and verification of convergence for hierarc...

Methods and apparatus to simulate metastability for circuit design...

Method for comprehensive integration verification of mixed-signal c...

Methods and apparatus to simulate metastability for circuit design...

Method for comprehensive integration verification of mixed-signal c...

Method for comprehensive integration verification of mixed-signal c...

Method for comprehensive integration verification of mixed-signal c...

Prefetch termination at powered down memory bank boundary in shared...

Multiprocessor system power management of shared memories powering...

Power management in federated/distributed shared memory architecture

Patents Applicationslast 30 patents

MANAGING CLOCK TRIGGER SIGNALS FOR ASYNCHRONOUS CLOCK DOMAINS

DYNAMIC CONTROL OF A MULTI-TRIM OSCILLATOR

TRACKING COVERAGE ARTIFACTS FOR PERIODIC SIGNALS USING SEQUENCE-BAS...

HIERARCHICAL CDC AND RDC VERIFICATION

TECHNIQUES FOR MODELING AND VERIFICATION OF CONVERGENCE FOR HIERARC...

IDENTIFYING GLITCHES AND LEVELS IN MIXED-SIGNAL WAVEFORMS

TECHNIQUES FOR DESIGN VERIFICATION OF DOMAIN CROSSINGS

METHODS AND APPARATUS TO SIMULATE METASTABILITY FOR CIRCUIT DESIGN...

METHODS AND APPARATUS TO SIMULATE METASTABILITY FOR CIRCUIT DESIGN...

METHOD FOR COMPREHENSIVE INTEGRATION VERIFICATION OF MIXED-SIGNAL C...

METHOD FOR COMPREHENSIVE INTEGRATION VERIFICATION OF MIXED-SIGNAL C...

METHOD FOR COMPREHENSIVE INTEGRATION VERIFICATION OF MIXED-SIGNAL C...

METHOD FOR COMPREHENSIVE INTEGRATION VERIFICATION OF MIXED-SIGNAL C...

Hardware Controlled Power Management of Shared Memories

Power Management in Federated/Distributed Shared Memory Architecture

Prefetch Termination at Powered Down Memory Bank Boundary in Shared...