Sudhir D. Kadkade

Person

Lake Oswego, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
System to combat design-time vulnerability
- Patent number 9,984,193
- Issue date May 29, 2018
- Mentor Graphics Corporation
- Serge Leef
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input space reduction for verification test set generation
- Patent number 9,619,598
- Issue date Apr 11, 2017
- Mentor Graphics Corporation
- Clifton A. Lyons
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input space reduction for verification test set generation
- Patent number 9,135,376
- Issue date Sep 15, 2015
- Mentor Graphics Corporation
- Sudhir D. Kadkade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System to combat design-time vulnerability
- Patent number 8,930,878
- Issue date Jan 6, 2015
- Mentor Graphics Corporation
- Serge Leef
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic verification traversal strategies
- Patent number 7,549,100
- Issue date Jun 16, 2009
- Sudhir Dattaram Kadkade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System verification using one or more automata
- Patent number 7,290,193
- Issue date Oct 30, 2007
- Sudhir Dattaram Kadkade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resource management during system verification
- Patent number 7,234,093
- Issue date Jun 19, 2007
- Sudhir Dattaram Kadkade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automaton synchronization during system verification
- Patent number 7,234,094
- Issue date Jun 19, 2007
- Sudhir Dattaram Kadkade
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TEST CASE GENERATION USING A CONSTRAINT GRAPH SOLVER
- Publication number 20170220455
- Publication date Aug 3, 2017
- Mentor Graphics Corporation
- Ahmed Badran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Input Space Reduction for Verification Test Set Generation
- Publication number 20140013290
- Publication date Jan 9, 2014
- Mentor Graphics Corporation
- Clifton A. Lyons
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Input Space Reduction for Verification Test Set Generation
- Publication number 20130298102
- Publication date Nov 7, 2013
- Mentor Graphics Corporation
- Sudhir D. Kadkade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coverage Based Pairwise Test Set Generation for Verification of Ele...
- Publication number 20130007680
- Publication date Jan 3, 2013
- SUDHIR D. KADKADE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC VERIFICATION TRAVERSAL STRATEGIES
- Publication number 20080059842
- Publication date Mar 6, 2008
- Sudhir Dattaram Kadkade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automaton synchronization during system verification
- Publication number 20050081094
- Publication date Apr 14, 2005
- Lighthouse Design Atomation, Inc.
- Sudhir Dattaram Kadkade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resource management during system verification
- Publication number 20050081103
- Publication date Apr 14, 2005
- Lighthouse Design Automation, Inc.
- Sudhir Dattaram Kadkade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for programming devices using finite state machin...
- Publication number 20030066050
- Publication date Apr 3, 2003
- Douglas W. Wang
- G05 - CONTROLLING REGULATING

Sudhir D. Kadkade

Person

Patents Grantslast 30 patents

System to combat design-time vulnerability

Input space reduction for verification test set generation

Input space reduction for verification test set generation

System to combat design-time vulnerability

Dynamic verification traversal strategies

System verification using one or more automata

Resource management during system verification

Automaton synchronization during system verification

Patents Applicationslast 30 patents

TEST CASE GENERATION USING A CONSTRAINT GRAPH SOLVER

Input Space Reduction for Verification Test Set Generation

Input Space Reduction for Verification Test Set Generation

Coverage Based Pairwise Test Set Generation for Verification of Ele...

DYNAMIC VERIFICATION TRAVERSAL STRATEGIES

Automaton synchronization during system verification

Resource management during system verification

Method and system for programming devices using finite state machin...