Sudipta Bhawmik

Person

Princeton, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and system for improving the test quality for scan-based BIS...
- Patent number 6,694,466
- Issue date Feb 17, 2004
- Agere Systems Inc.
- Huan-Chih Tsai
- G01 - MEASURING TESTING
Information Patent Grant
Method for implementing a bist scheme into integrated circuits for...
- Patent number 6,463,560
- Issue date Oct 8, 2002
- Agere Systems Guardian Corp.
- Sudipta Bhawmik
- G01 - MEASURING TESTING
Information Patent Grant
Almost full-scan BIST method and system having higher fault coverag...
- Patent number 6,463,561
- Issue date Oct 8, 2002
- Agere Systems Guardian Corp.
- Sudipta Bhawmik
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for partitioning long scan chains in scan base...
- Patent number 6,370,664
- Issue date Apr 9, 2002
- Agere Systems Guardian Corp.
- Sudipta Bhawmik
- G01 - MEASURING TESTING
Information Patent Grant
Hybrid algorithm for test point selection for scan-based BIST
- Patent number 6,256,759
- Issue date Jul 3, 2001
- Agere Systems Inc.
- Sudipta Bhawmik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bist architecture for detecting path-delay faults in a sequential c...
- Patent number 6,148,425
- Issue date Nov 14, 2000
- Lucent Technologies Inc.
- Sudipta Bhawmik
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for built-in self-test with multiple clock cir...
- Patent number 5,680,543
- Issue date Oct 21, 1997
- Lucent Technologies Inc.
- Sudipta Bhawmik
- G01 - MEASURING TESTING

Sudipta Bhawmik

Person

Patents Grantslast 30 patents

Method and system for improving the test quality for scan-based BIS...

Method for implementing a bist scheme into integrated circuits for...

Almost full-scan BIST method and system having higher fault coverag...

Method and apparatus for partitioning long scan chains in scan base...

Hybrid algorithm for test point selection for scan-based BIST

Bist architecture for detecting path-delay faults in a sequential c...

Method and apparatus for built-in self-test with multiple clock cir...