Sujat Jamil

Person

Gilbert, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Interconnected ring network in a multi-processor system
- Patent number 10,230,542
- Issue date Mar 12, 2019
- Marvell World Trade Ltd.
- Eitan Joshua
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to use hardware alias detection and management...
- Patent number 9,934,152
- Issue date Apr 3, 2018
- Marvell International Ltd.
- Richard Bryant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for use of a preload instruction to improve ef...
- Patent number 9,892,051
- Issue date Feb 13, 2018
- Marvell International Ltd.
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing aliasing in a virtually indexed physically tagged cache
- Patent number 9,842,051
- Issue date Dec 12, 2017
- Marvell International Ltd.
- Kim Schuttenberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for sharing instruction scheduling resources a...
- Patent number 9,606,800
- Issue date Mar 28, 2017
- Marvell International Ltd.
- Tom Hameenanttila
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnected ring network in a multi-processor system
- Patent number 9,454,480
- Issue date Sep 27, 2016
- Marvell World Trade Ltd.
- Eitan Joshua
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for processing speculative, out-of-order memor...
- Patent number 9,442,735
- Issue date Sep 13, 2016
- Marvell International Ltd.
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread-aware cache memory management
- Patent number 9,223,709
- Issue date Dec 29, 2015
- Marvell International Ltd.
- R. Frank O'Bleness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for reducing interrupt latency
- Patent number 9,116,742
- Issue date Aug 25, 2015
- Marvell International Ltd.
- Kim Schuttenberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for associating requests and responses with id...
- Patent number 9,086,976
- Issue date Jul 21, 2015
- Marvell International Ltd.
- R. Frank O'Bleness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus having a snoop filter decoupled from an associ...
- Patent number 9,058,272
- Issue date Jun 16, 2015
- Marvell International Ltd.
- Frank O'Bleness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Detecting and reissuing of loop instructions in reorder structure
- Patent number 9,026,769
- Issue date May 5, 2015
- Marvell International Ltd.
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory bank selection
- Patent number 8,990,505
- Issue date Mar 24, 2015
- Marvell International Ltd.
- Sujat Jamil
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for improving cache efficiency
- Patent number 8,943,273
- Issue date Jan 27, 2015
- Marvell International Ltd.
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative scheduling of memory instructions in out-of-order proce...
- Patent number 8,918,625
- Issue date Dec 23, 2014
- Marvell International Ltd.
- R. Frank O'Bleness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic pipeline reconfiguration including changing a number of stages
- Patent number 8,806,181
- Issue date Aug 12, 2014
- Marvell International Ltd
- R. Frank O'Bleness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable cache access protocol to optimize power consumption an...
- Patent number 8,769,204
- Issue date Jul 1, 2014
- Marvell International Ltd.
- Joseph Delgross
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for associating requests and responses with id...
- Patent number 8,688,919
- Issue date Apr 1, 2014
- Marvell International Ltd.
- R. Frank O'Bleness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic logic and shifting device for use in a processor
- Patent number 8,688,761
- Issue date Apr 1, 2014
- QUALCOMM Incorporated
- Muhammad Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Way-selecting translation lookaside buffer
- Patent number 8,631,206
- Issue date Jan 14, 2014
- Marvell International Ltd.
- R. Frank O'Bleness
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Implementing direct access caches in coherent multiprocessors
- Patent number 8,533,401
- Issue date Sep 10, 2013
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable cache access protocol to optimize power consumption an...
- Patent number 8,458,404
- Issue date Jun 4, 2013
- Marvell International Ltd.
- Joseph Delgross
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for data-less bus query
- Patent number 8,296,525
- Issue date Oct 23, 2012
- Marvell International Ltd.
- Frank O'Bleness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to translate virtual addresses to physical add...
- Patent number 8,195,916
- Issue date Jun 5, 2012
- QUALCOMM Incorporated
- Paul Douglas Bassett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for hardware-configurable multi-policy coheren...
- Patent number 8,135,916
- Issue date Mar 13, 2012
- Marvell International Ltd.
- R. Frank O'Bleness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic logic and shifting device for use in a processor
- Patent number 8,099,448
- Issue date Jan 17, 2012
- QUALCOMM Incorporated
- Muhammad Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power optimized replay of blocked operations in a pipilined archite...
- Patent number 7,966,477
- Issue date Jun 21, 2011
- Marvell International Ltd.
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for variable thread allocation and switching in a...
- Patent number 7,917,907
- Issue date Mar 29, 2011
- QUALCOMM Incorporated
- Muhammad Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling execution mode of program threads by applying a mask to...
- Patent number 7,849,466
- Issue date Dec 7, 2010
- QUALCOMM Incorporated
- Lucian Codrescu
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Apparatus and method for arbitrating heterogeneous agents in on-chi...
- Patent number 7,765,349
- Issue date Jul 27, 2010
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM
- Publication number 20170180156
- Publication date Jun 22, 2017
- Marvell World Trade Ltd.
- Eitan Joshua
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM
- Publication number 20140201326
- Publication date Jul 17, 2014
- Marvell World Trade Ltd.
- Eitan Joshua
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM
- Publication number 20140201445
- Publication date Jul 17, 2014
- Marvell World Trade Ltd.
- Eitan Joshua
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARITHMETIC LOGIC AND SHIFTING DEVICE FOR USE IN A PROCESSOR
- Publication number 20120083912
- Publication date Apr 5, 2012
- QUALCOMM Incorporated
- Muhammad Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method to Translate Virtual Addresses to Physical Add...
- Publication number 20100228944
- Publication date Sep 9, 2010
- QUALCOMM Incorporated
- Paul Douglas Bassett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Apparatus for Early Fixed Latency Subtractive Decoding
- Publication number 20080282008
- Publication date Nov 13, 2008
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLEMENTING HETEROGENEOUS INTERCONNECTS
- Publication number 20080250168
- Publication date Oct 9, 2008
- Intel Corporation
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND APPARATUS FOR EARLY FIXED LATENCY SUBTRACTIVE DECODING
- Publication number 20070186019
- Publication date Aug 9, 2007
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for fixed latency subtractive decoding
- Publication number 20070162672
- Publication date Jul 12, 2007
- Marvell International Ltd.
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Arithmethic logic and shifting device for use in a processor
- Publication number 20070100923
- Publication date May 3, 2007
- Qualcomm Incorporated
- Muhammad Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pointer computation method and system for a scalable, programmable...
- Publication number 20070094478
- Publication date Apr 26, 2007
- Erich Plondke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method of controlling multiple program threads within a...
- Publication number 20070016759
- Publication date Jan 18, 2007
- Lucian Codrescu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power microprocessor cache memory and method of operation
- Publication number 20060268592
- Publication date Nov 30, 2006
- Baker Mohammad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for supporting heterogeneous agents in on-chip...
- Publication number 20060271716
- Publication date Nov 30, 2006
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for variable thread allocation and switching in a...
- Publication number 20060218559
- Publication date Sep 28, 2006
- Muhammad Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processor and method of grouping and executing dependent instructio...
- Publication number 20060212681
- Publication date Sep 21, 2006
- Lucian Codrescu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Variable interleaved multithreaded processor method and system
- Publication number 20060206902
- Publication date Sep 14, 2006
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for providing a low power mode for a processor...
- Publication number 20060143409
- Publication date Jun 29, 2006
- Quinn W. Merrell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dirty line hint array for cache flushing
- Publication number 20060143397
- Publication date Jun 29, 2006
- R. Frank O'Bleness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for implementing heterogeneous interconnects
- Publication number 20060143358
- Publication date Jun 29, 2006
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques for pushing data to a processor cache
- Publication number 20060112238
- Publication date May 25, 2006
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Direct processor cache access within a system having a coherent mul...
- Publication number 20060004961
- Publication date Jan 5, 2006
- Steven J. Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Direct processor cache access within a system having a coherent mul...
- Publication number 20060004965
- Publication date Jan 5, 2006
- Steven J. Tu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pushing of clean data to one or more processors in a system having...
- Publication number 20050289303
- Publication date Dec 29, 2005
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method for supporting heterogeneous agents in on-chip...
- Publication number 20050216632
- Publication date Sep 29, 2005
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache memory to support a processor's power mode of operation
- Publication number 20050204195
- Publication date Sep 15, 2005
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache memory to support a processor's power mode of operation
- Publication number 20050204202
- Publication date Sep 15, 2005
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache memory to support a processor's power mode of operation
- Publication number 20050193176
- Publication date Sep 1, 2005
- Samantha J. Edirisooriya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for cache intervention
- Publication number 20050166020
- Publication date Jul 28, 2005
- Intel Corporation
- Sujat Jamil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus to dispatch interrupts in multi-processor sys...
- Publication number 20050125582
- Publication date Jun 9, 2005
- Steven J. Tu
- G06 - COMPUTING CALCULATING COUNTING

Sujat Jamil

Person

Patents Grantslast 30 patents

Interconnected ring network in a multi-processor system

Method and apparatus to use hardware alias detection and management...

Method and apparatus for use of a preload instruction to improve ef...

Managing aliasing in a virtually indexed physically tagged cache

Method and apparatus for sharing instruction scheduling resources a...

Interconnected ring network in a multi-processor system

Method and apparatus for processing speculative, out-of-order memor...

Thread-aware cache memory management

Systems and methods for reducing interrupt latency

Method and apparatus for associating requests and responses with id...

Method and apparatus having a snoop filter decoupled from an associ...

Detecting and reissuing of loop instructions in reorder structure

Cache memory bank selection

Method and apparatus for improving cache efficiency

Speculative scheduling of memory instructions in out-of-order proce...

Dynamic pipeline reconfiguration including changing a number of stages

Programmable cache access protocol to optimize power consumption an...

Method and apparatus for associating requests and responses with id...

Arithmetic logic and shifting device for use in a processor

Way-selecting translation lookaside buffer

Implementing direct access caches in coherent multiprocessors

Programmable cache access protocol to optimize power consumption an...

Method and apparatus for data-less bus query

Apparatus and method to translate virtual addresses to physical add...

Method and apparatus for hardware-configurable multi-policy coheren...

Arithmetic logic and shifting device for use in a processor

Power optimized replay of blocked operations in a pipilined archite...

Method and system for variable thread allocation and switching in a...

Controlling execution mode of program threads by applying a mask to...

Apparatus and method for arbitrating heterogeneous agents in on-chi...

Patents Applicationslast 30 patents

INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM

INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM

INTERCONNECTED RING NETWORK IN A MULTI-PROCESSOR SYSTEM

ARITHMETIC LOGIC AND SHIFTING DEVICE FOR USE IN A PROCESSOR

Apparatus and Method to Translate Virtual Addresses to Physical Add...

System and Apparatus for Early Fixed Latency Subtractive Decoding

METHOD AND APPARATUS FOR IMPLEMENTING HETEROGENEOUS INTERCONNECTS

SYSTEM AND APPARATUS FOR EARLY FIXED LATENCY SUBTRACTIVE DECODING

Method and apparatus for fixed latency subtractive decoding

Arithmethic logic and shifting device for use in a processor

Pointer computation method and system for a scalable, programmable...

System and method of controlling multiple program threads within a...

Low power microprocessor cache memory and method of operation

Apparatus and method for supporting heterogeneous agents in on-chip...

Method and system for variable thread allocation and switching in a...

Processor and method of grouping and executing dependent instructio...

Variable interleaved multithreaded processor method and system

Method and apparatus for providing a low power mode for a processor...

Dirty line hint array for cache flushing

Method and apparatus for implementing heterogeneous interconnects

Techniques for pushing data to a processor cache

Direct processor cache access within a system having a coherent mul...

Direct processor cache access within a system having a coherent mul...

Pushing of clean data to one or more processors in a system having...

Apparatus and method for supporting heterogeneous agents in on-chip...

Cache memory to support a processor's power mode of operation

Cache memory to support a processor's power mode of operation

Cache memory to support a processor's power mode of operation

Methods and apparatus for cache intervention

Methods and apparatus to dispatch interrupts in multi-processor sys...