Sujit Sharan

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Metal-free frame design for silicon bridges for semiconductor packages
- Patent number 12,170,253
- Issue date Dec 17, 2024
- Intel Corporation
- Dae-Woo Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Guard ring design enabling in-line testing of silicon bridges for s...
- Patent number 12,142,553
- Issue date Nov 12, 2024
- Intel Corporation
- Arnab Sarkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested architectures for enhanced heterogeneous integration
- Patent number 12,142,545
- Issue date Nov 12, 2024
- Intel Corporation
- Ravindranath Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip package and method of providing die-to-die interconnects...
- Patent number 12,113,026
- Issue date Oct 8, 2024
- Intel Corporation
- Henning Braunisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal-free frame design for silicon bridges for semiconductor packages
- Patent number 12,074,121
- Issue date Aug 27, 2024
- Intel Corporation
- Dae-Woo Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package design scheme for enabling high-speed low-loss signaling an...
- Patent number 12,057,413
- Issue date Aug 6, 2024
- Intel Corporation
- Lijiang Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor die embedded in package substrate for providing capacitan...
- Patent number 12,046,568
- Issue date Jul 23, 2024
- Intel Corporation
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip package and method of providing die-to-die interconnects...
- Patent number 11,876,053
- Issue date Jan 16, 2024
- Intel Corporation
- Henning Braunisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alternative surfaces for conductive pad layers of silicon bridges f...
- Patent number 11,848,259
- Issue date Dec 19, 2023
- Intel Corporation
- Dae-Woo Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-chip package and method of providing die-to-die interconnects...
- Patent number 11,824,008
- Issue date Nov 21, 2023
- Intel Corporation
- Henning Braunisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested architectures for enhanced heterogeneous integration
- Patent number 11,798,865
- Issue date Oct 24, 2023
- Intel Corporation
- Ravindranath Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Rounded metal trace corner for stress reduction
- Patent number 11,784,150
- Issue date Oct 10, 2023
- Intel Corporation
- Dae-Woo Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nested architectures for enhanced heterogeneous integration
- Patent number 11,742,261
- Issue date Aug 29, 2023
- Intel Corporation
- Ravindranath Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor die embedded in package substrate for providing capacitan...
- Patent number 11,728,294
- Issue date Aug 15, 2023
- Intel Corporation
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Horizontal pitch translation using embedded bridge dies
- Patent number 11,694,952
- Issue date Jul 4, 2023
- Intel Corporation
- Sujit Sharan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Guard ring design enabling in-line testing of silicon bridges for s...
- Patent number 11,676,889
- Issue date Jun 13, 2023
- Intel Corporation
- Arnab Sarkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal-free frame design for silicon bridges for semiconductor packages
- Patent number 11,626,372
- Issue date Apr 11, 2023
- Intel Corporation
- Dae-Woo Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect hub for dies
- Patent number 11,621,223
- Issue date Apr 4, 2023
- Intel Corporation
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bridge hub tiling architecture
- Patent number 11,569,173
- Issue date Jan 31, 2023
- Intel Corporation
- Andrew P. Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilevel die complex with integrated discrete passive components
- Patent number 11,462,521
- Issue date Oct 4, 2022
- Intel Corporation
- Andrew P. Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded very high density (VHD) layer
- Patent number 11,387,187
- Issue date Jul 12, 2022
- Intel Corporation
- Andrew Paul Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Rounded metal trace corner for stress reduction
- Patent number 11,380,643
- Issue date Jul 5, 2022
- Intel Corporation
- Dae-Woo Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device, method and system for providing recessed interconnect struc...
- Patent number 11,355,427
- Issue date Jun 7, 2022
- Intel Corporation
- Howe Yin Loo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EMIB copper layer for signal and power routing
- Patent number 11,322,445
- Issue date May 3, 2022
- Intel Corporation
- Yidnekachew S. Mekonnen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Horizontal pitch translation using embedded bridge dies
- Patent number 11,276,635
- Issue date Mar 15, 2022
- Intel Corporation
- Sujit Sharan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Guard ring design enabling in-line testing of silicon bridges for s...
- Patent number 11,257,743
- Issue date Feb 22, 2022
- Intel Corporation
- Arnab Sarkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-inductance current paths for on-package power distributions and...
- Patent number 11,222,837
- Issue date Jan 11, 2022
- Intel Corporation
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enabling long interconnect bridges
- Patent number 11,222,847
- Issue date Jan 11, 2022
- Intel Corporation
- Ravindranath V. Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor die embedded in package substrate for providing capacitan...
- Patent number 11,195,805
- Issue date Dec 7, 2021
- Intel Corporation
- Andrew Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Signal routing carrier
- Patent number 11,114,394
- Issue date Sep 7, 2021
- Intel Corporation
- Lijiang Wang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTERCONNECT BRIDGE CIRCUITRY DESIGNS FOR INTEGRATED CIRCUIT PACKAG...
- Publication number 20240332193
- Publication date Oct 3, 2024
- Intel Corporation
- Lijiang Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITAN...
- Publication number 20240321785
- Publication date Sep 26, 2024
- Intel Corporation
- Andrew COLLINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
- Publication number 20240128162
- Publication date Apr 18, 2024
- Intel Corporation
- Ravindranath MAHAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALTERNATIVE SURFACES FOR CONDUCTIVE PAD LAYERS OF SILICON BRIDGES F...
- Publication number 20240071884
- Publication date Feb 29, 2024
- Intel Corporation
- Dae-Woo KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS...
- Publication number 20240038671
- Publication date Feb 1, 2024
- Intel Corporation
- Henning BRAUNISCH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT BRIDGE WITH SIMILAR CHANNEL LENGTHS
- Publication number 20240006323
- Publication date Jan 4, 2024
- Intel Corporation
- Lijiang Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYER SELECTION FOR ROUTING HIGH-SPEED SIGNALS IN SUBSTRATES
- Publication number 20240006286
- Publication date Jan 4, 2024
- Intel Corporation
- Arghya Sain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
- Publication number 20230411245
- Publication date Dec 21, 2023
- Intel Corporation
- Ravindranath MAHAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITAN...
- Publication number 20230343731
- Publication date Oct 26, 2023
- Intel Corporation
- Andrew COLLINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PASSIVE ELECTRICAL COMPONENTS IN MOLD METAL LAYERS OF A MULTI-DIE C...
- Publication number 20230299044
- Publication date Sep 21, 2023
- Intel Corporation
- Andrew P. Collins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...
- Publication number 20230260884
- Publication date Aug 17, 2023
- Intel Corporation
- Arnab SARKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES
- Publication number 20230238339
- Publication date Jul 27, 2023
- Intel Corporation
- Dae-Woo KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES
- Publication number 20230223361
- Publication date Jul 13, 2023
- Intel Corporation
- Dae-Woo KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION
- Publication number 20230133429
- Publication date May 4, 2023
- Intel Corporation
- Ravindranath MAHAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BRIDGE HUB TILING ARCHITECTURE
- Publication number 20230138386
- Publication date May 4, 2023
- Intel Corporation
- ANDREW P. COLLINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS...
- Publication number 20230016326
- Publication date Jan 19, 2023
- Intel Corporation
- Henning M. Braunisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROUNDED METAL TRACE CORNER FOR STRESS REDUCTION
- Publication number 20220285306
- Publication date Sep 8, 2022
- Intel Corporation
- Dae-Woo KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES
- Publication number 20220155539
- Publication date May 19, 2022
- Intel Corporation
- Srinivas V. PIETAMBARAM
- G02 - OPTICS
Information Patent Application
HORIZONTAL PITCH TRANSLATION USING EMBEDDED BRIDGE DIES
- Publication number 20220157706
- Publication date May 19, 2022
- Intel Corporation
- Sujit SHARAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENABLING LONG INTERCONNECT BRIDGES
- Publication number 20220130763
- Publication date Apr 28, 2022
- Intel Corporation
- Ravindranath V. Mahajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...
- Publication number 20220130743
- Publication date Apr 28, 2022
- Intel Corporation
- Arnab SARKAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITAN...
- Publication number 20220059476
- Publication date Feb 24, 2022
- Intel Corporation
- Andrew COLLINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMIB COPPER LAYER FOR SIGNAL AND POWER ROUTING
- Publication number 20210296240
- Publication date Sep 23, 2021
- Yidnekachew S. Mekonnen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EMIB ARCHITECTURE WITH DEDICATED METAL LAYERS FOR IMPROVING POWER D...
- Publication number 20210280518
- Publication date Sep 9, 2021
- Intel Corporation
- Jianyong XIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS...
- Publication number 20210134726
- Publication date May 6, 2021
- Intel Corporation
- Henning BRAUNISCH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES
- Publication number 20210125942
- Publication date Apr 29, 2021
- Intel Corporation
- Dae-Woo KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIGNAL ROUTING CARRIER
- Publication number 20210043588
- Publication date Feb 11, 2021
- Intel Corporation
- Lijiang Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ROUNDED METAL TRACE CORNER FOR STRESS REDUCTION
- Publication number 20200402940
- Publication date Dec 24, 2020
- Intel Corporation
- Dae-Woo KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATELESS DOUBLE-SIDED EMBEDDED MULTI-DIE INTERCONNECT BRIDGE
- Publication number 20200395300
- Publication date Dec 17, 2020
- Intel Corporation
- Biancun Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HORIZONTAL PITCH TRANSLATION USING EMBEDDED BRIDGE DIES
- Publication number 20200381350
- Publication date Dec 3, 2020
- Intel Corporation
- Sujit SHARAN
- H01 - BASIC ELECTRIC ELEMENTS

Sujit Sharan

Person

Patents Grantslast 30 patents

Metal-free frame design for silicon bridges for semiconductor packages

Guard ring design enabling in-line testing of silicon bridges for s...

Nested architectures for enhanced heterogeneous integration

Multi-chip package and method of providing die-to-die interconnects...

Metal-free frame design for silicon bridges for semiconductor packages

Package design scheme for enabling high-speed low-loss signaling an...

Capacitor die embedded in package substrate for providing capacitan...

Multi-chip package and method of providing die-to-die interconnects...

Alternative surfaces for conductive pad layers of silicon bridges f...

Multi-chip package and method of providing die-to-die interconnects...

Nested architectures for enhanced heterogeneous integration

Rounded metal trace corner for stress reduction

Nested architectures for enhanced heterogeneous integration

Capacitor die embedded in package substrate for providing capacitan...

Horizontal pitch translation using embedded bridge dies

Guard ring design enabling in-line testing of silicon bridges for s...

Metal-free frame design for silicon bridges for semiconductor packages

Interconnect hub for dies

Bridge hub tiling architecture

Multilevel die complex with integrated discrete passive components

Embedded very high density (VHD) layer

Rounded metal trace corner for stress reduction

Device, method and system for providing recessed interconnect struc...

EMIB copper layer for signal and power routing

Horizontal pitch translation using embedded bridge dies

Guard ring design enabling in-line testing of silicon bridges for s...

Low-inductance current paths for on-package power distributions and...

Enabling long interconnect bridges

Capacitor die embedded in package substrate for providing capacitan...

Signal routing carrier

Patents Applicationslast 30 patents

INTERCONNECT BRIDGE CIRCUITRY DESIGNS FOR INTEGRATED CIRCUIT PACKAG...

CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITAN...

NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION

ALTERNATIVE SURFACES FOR CONDUCTIVE PAD LAYERS OF SILICON BRIDGES F...

MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS...

INTERCONNECT BRIDGE WITH SIMILAR CHANNEL LENGTHS

LAYER SELECTION FOR ROUTING HIGH-SPEED SIGNALS IN SUBSTRATES

NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION

CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITAN...

PASSIVE ELECTRICAL COMPONENTS IN MOLD METAL LAYERS OF A MULTI-DIE C...

GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

NESTED ARCHITECTURES FOR ENHANCED HETEROGENEOUS INTEGRATION

BRIDGE HUB TILING ARCHITECTURE

MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS...

ROUNDED METAL TRACE CORNER FOR STRESS REDUCTION

HIGH BANDWIDTH OPTICAL INTERCONNECTION ARCHITECTURES

HORIZONTAL PITCH TRANSLATION USING EMBEDDED BRIDGE DIES

ENABLING LONG INTERCONNECT BRIDGES

GUARD RING DESIGN ENABLING IN-LINE TESTING OF SILICON BRIDGES FOR S...

CAPACITOR DIE EMBEDDED IN PACKAGE SUBSTRATE FOR PROVIDING CAPACITAN...

EMIB COPPER LAYER FOR SIGNAL AND POWER ROUTING

EMIB ARCHITECTURE WITH DEDICATED METAL LAYERS FOR IMPROVING POWER D...

MULTI-CHIP PACKAGE AND METHOD OF PROVIDING DIE-TO-DIE INTERCONNECTS...

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

SIGNAL ROUTING CARRIER

ROUNDED METAL TRACE CORNER FOR STRESS REDUCTION

SUBSTRATELESS DOUBLE-SIDED EMBEDDED MULTI-DIE INTERCONNECT BRIDGE

HORIZONTAL PITCH TRANSLATION USING EMBEDDED BRIDGE DIES