Sujoy Chinmoy Chakravarty

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus for managing clock duty cycle correction
- Patent number 9,584,108
- Issue date Feb 28, 2017
- SILAB TECH PVT. LTD.
- Sujoy Chakravarty
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for managing estimation and calibration of non...
- Patent number 9,548,855
- Issue date Jan 17, 2017
- SILAB TECH PVT. LTD.
- Biman Chattopadhyay
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast locking clock and data recovery using only two samples per period
- Patent number 9,407,424
- Issue date Aug 2, 2016
- Texas Instruments Incorporated
- Bharathi Rahuldev Holla
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Architecture for VBUS pulsing in UDSM processes
- Patent number 9,065,430
- Issue date Jun 23, 2015
- Texas Instruments Incorporated
- Sumantra Seth
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Architecture for VBUS pulsing in UDSM processes
- Patent number 8,704,550
- Issue date Apr 22, 2014
- Texas Instruments Incorporated
- Sumantra Seth
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Phase interpolator and a delay circuit for the phase interpolator
- Patent number 8,446,198
- Issue date May 21, 2013
- Texas Instruments Incorporated
- Anant Shankar Kamath
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast-locking delay locked loop
- Patent number 8,085,074
- Issue date Dec 27, 2011
- Texas Instruments Incorporated
- Jayawardan Janardhanan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronous clock multiplexing and output-enable
- Patent number 8,054,103
- Issue date Nov 8, 2011
- Texas Instruments Incorporated
- Jayawardan Janardhanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constant output common mode voltage of a pre-amplifier circuit
- Patent number 7,683,716
- Issue date Mar 23, 2010
- Texas Instruments Incorporated
- Ravi Jitendra Mehta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed, high common mode range, low delay comparator input stage
- Patent number 6,703,872
- Issue date Mar 9, 2004
- Texas Instruments Incorporated
- Sujoy Chakravarty
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
TRANSCEIVER DEVICES WITH TRANSMITTER AND RECEIVER FREQUENCY CONTROL
- Publication number 20230141608
- Publication date May 11, 2023
- Synopsys, Inc.
- Gopal Krishna Ullal NAYAK
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPARATUS FOR MANAGING CLOCK DUTY CYCLE CORRECTION (DCC)
- Publication number 20160087620
- Publication date Mar 24, 2016
- SUJOY CHAKRAVARTY
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR MANAGING ESTIMATION AND CALIBRATION OF NON...
- Publication number 20160056949
- Publication date Feb 25, 2016
- BIMAN CHATTOPADHYAY
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DUTY CYCLE CORRECTION CIRCUIT
- Publication number 20140266361
- Publication date Sep 18, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Siddharth Shashidharan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES
- Publication number 20140247071
- Publication date Sep 4, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Sumantra Seth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE INTERPOLATOR AND A DELAY CIRCUIT FOR THE PHASE INTERPOLATOR
- Publication number 20110254603
- Publication date Oct 20, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Anant Shankar KAMATH
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONSTANT OUTPUT COMMON MODE VOLTAGE OF A PRE-AMPLIFIER CIRCUIT
- Publication number 20090302895
- Publication date Dec 10, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Ravi Jitendra Mehta
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES
- Publication number 20090140772
- Publication date Jun 4, 2009
- Sumantra Seth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High speed, high common mode range, low delay comparator input stage
- Publication number 20030107409
- Publication date Jun 12, 2003
- Sujoy Chakravarty
- H03 - BASIC ELECTRONIC CIRCUITRY

Sujoy Chinmoy Chakravarty

Person

Patents Grantslast 30 patents

Apparatus for managing clock duty cycle correction

Method and apparatus for managing estimation and calibration of non...

Fast locking clock and data recovery using only two samples per period

Architecture for VBUS pulsing in UDSM processes

Architecture for VBUS pulsing in UDSM processes

Phase interpolator and a delay circuit for the phase interpolator

Fast-locking delay locked loop

Synchronous clock multiplexing and output-enable

Constant output common mode voltage of a pre-amplifier circuit

High speed, high common mode range, low delay comparator input stage

Patents Applicationslast 30 patents

TRANSCEIVER DEVICES WITH TRANSMITTER AND RECEIVER FREQUENCY CONTROL

APPARATUS FOR MANAGING CLOCK DUTY CYCLE CORRECTION (DCC)

METHOD AND APPARATUS FOR MANAGING ESTIMATION AND CALIBRATION OF NON...

DUTY CYCLE CORRECTION CIRCUIT

ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES

PHASE INTERPOLATOR AND A DELAY CIRCUIT FOR THE PHASE INTERPOLATOR

CONSTANT OUTPUT COMMON MODE VOLTAGE OF A PRE-AMPLIFIER CIRCUIT

ARCHITECTURE FOR VBUS PULSING IN UDSM PROCESSES

High speed, high common mode range, low delay comparator input stage