Sumanth Katte Gururajarao

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low power clock gating circuit
- Patent number 9,148,145
- Issue date Sep 29, 2015
- MediaTek Singapore Pte Ltd.
- Sumanth Katte Gururajarao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power clock gating circuit
- Patent number 8,981,815
- Issue date Mar 17, 2015
- MediaTek Singapore Pte Ltd.
- Sumanth Katte Gururajarao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for reading data from a memory array
- Patent number 7,773,431
- Issue date Aug 10, 2010
- Texas Instruments Incorporated
- Radu Avramescu
- G11 - INFORMATION STORAGE
Information Patent Grant
Slave latch controlled retention flop with lower leakage and higher...
- Patent number 7,652,513
- Issue date Jan 26, 2010
- Texas Instruments Incorporated
- Bindu Prabhakar Rao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Ultra low area overhead retention flip-flop for power-down applicat...
- Patent number 7,639,056
- Issue date Dec 29, 2009
- Texas Instruments Incorporated
- Sumanth Katte Gururajarao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dual mode SRAM architecture for voltage scaling and power management
- Patent number 7,630,270
- Issue date Dec 8, 2009
- Texas Instruments Incorporated
- Uming Ko
- G11 - INFORMATION STORAGE
Information Patent Grant
Power savings with a level-shifting boundary isolation flip-flop (L...
- Patent number 7,622,955
- Issue date Nov 24, 2009
- Texas Instruments Incorporated
- Ramaprasath Vilangudipitchai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Performance and area scalable cell architecture technology
- Patent number 7,564,077
- Issue date Jul 21, 2009
- Texas Instruments Incorporated
- Uming Ko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Representing data having multi-dimensional input vectors and corres...
- Patent number 7,483,819
- Issue date Jan 27, 2009
- Texas Instruments Incorporated
- Girishankar Gurumurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for reading data from a memory array
- Patent number 7,477,551
- Issue date Jan 13, 2009
- Texas Instruments Incorporated
- Radu Avramescu
- G11 - INFORMATION STORAGE
Information Patent Grant
Selectable application of offset to dynamically controlled voltage...
- Patent number 7,327,185
- Issue date Feb 5, 2008
- Texas Instruments Incorporated
- Hugh Mair
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Retention register for system-transparent state retention
- Patent number 7,091,766
- Issue date Aug 15, 2006
- Texas Instruments Incorporated
- Uming Ko
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Retention register with normal functionality independent of retenti...
- Patent number 6,989,702
- Issue date Jan 24, 2006
- Texas Instruments Incorporated
- Uming Ko
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric latch
- Patent number 6,947,310
- Issue date Sep 20, 2005
- Texas Instruments Incorporated
- Andrew Marshall
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Fast and Autonomous Mechanism for CPU OC Protection
- Publication number 20170068296
- Publication date Mar 9, 2017
- MEDIATEK SINGAPORE PTE LTD
- Hugh Thomas Mair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER CLOCK GATING CIRCUIT
- Publication number 20150155870
- Publication date Jun 4, 2015
- MEDIATEK SINGAPORE PTE LTD
- Sumanth Katte Gururajarao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER CLOCK GATING CIRCUIT
- Publication number 20140292372
- Publication date Oct 2, 2014
- MEDIATEK SINGAPORE PTE LTD
- Sumanth Katte Gururajarao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER SAVINGS WITH A LEVEL-SHIFTING BOUNDARY ISOLATION FLIP-FLOP (L...
- Publication number 20090262588
- Publication date Oct 22, 2009
- RAMAPRASATH VILANGUDIPITCHAI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR READING DATA FROM A MEMORY ARRAY
- Publication number 20090097327
- Publication date Apr 16, 2009
- Radu Avramescu
- G11 - INFORMATION STORAGE
Information Patent Application
Slave latch controlled retention flop with lower leakage and higher...
- Publication number 20090058484
- Publication date Mar 5, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Bindu Prabhakar Rao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS ME...
- Publication number 20090046519
- Publication date Feb 19, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Alice Wang
- G11 - INFORMATION STORAGE
Information Patent Application
Systems and methods for reading data from a memory array
- Publication number 20080123449
- Publication date May 29, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Radu Avramescu
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL MODE SRAM ARCHITECTURE FOR VOLTAGE SCALING AND POWER MANAGEMENT
- Publication number 20080043560
- Publication date Feb 21, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Uming Ko
- G11 - INFORMATION STORAGE
Information Patent Application
Performance and Area Scalable Cell Architecture Technology
- Publication number 20070290270
- Publication date Dec 20, 2007
- Uming Ko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ultra low area overhead retention flip-flop for power-down applicat...
- Publication number 20060267654
- Publication date Nov 30, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Sumanth Katte Gururajarao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Representing Data Having Multi-dimensional Input Vectors and Corres...
- Publication number 20060123074
- Publication date Jun 8, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Girishankar GURUMURTHY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selectable application of offset to dynamically controlled voltage...
- Publication number 20060091385
- Publication date May 4, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Hugh T. Mair
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Retention register with normal functionality independent of retenti...
- Publication number 20040051574
- Publication date Mar 18, 2004
- Uming Ko
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Rentention register for system-transparent state retention
- Publication number 20040008071
- Publication date Jan 15, 2004
- Uming Ko
- H03 - BASIC ELECTRONIC CIRCUITRY

Sumanth Katte Gururajarao

Person

Patents Grantslast 30 patents

Low power clock gating circuit

Low power clock gating circuit

Systems and methods for reading data from a memory array

Slave latch controlled retention flop with lower leakage and higher...

Ultra low area overhead retention flip-flop for power-down applicat...

Dual mode SRAM architecture for voltage scaling and power management

Power savings with a level-shifting boundary isolation flip-flop (L...

Performance and area scalable cell architecture technology

Representing data having multi-dimensional input vectors and corres...

Systems and methods for reading data from a memory array

Selectable application of offset to dynamically controlled voltage...

Retention register for system-transparent state retention

Retention register with normal functionality independent of retenti...

Ferroelectric latch

Patents Applicationslast 30 patents

Fast and Autonomous Mechanism for CPU OC Protection

LOW POWER CLOCK GATING CIRCUIT

LOW POWER CLOCK GATING CIRCUIT

POWER SAVINGS WITH A LEVEL-SHIFTING BOUNDARY ISOLATION FLIP-FLOP (L...

SYSTEMS AND METHODS FOR READING DATA FROM A MEMORY ARRAY

Slave latch controlled retention flop with lower leakage and higher...

METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS ME...

Systems and methods for reading data from a memory array

DUAL MODE SRAM ARCHITECTURE FOR VOLTAGE SCALING AND POWER MANAGEMENT

Performance and Area Scalable Cell Architecture Technology

Ultra low area overhead retention flip-flop for power-down applicat...

Representing Data Having Multi-dimensional Input Vectors and Corres...

Selectable application of offset to dynamically controlled voltage...

Retention register with normal functionality independent of retenti...

Rentention register for system-transparent state retention