Sundararajarao Mohan

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Blockchain machine compute acceleration engine with a block verify...
- Patent number 11,743,051
- Issue date Aug 29, 2023
- Xilinx, Inc.
- Haris Javaid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Blockchain machine network acceleration engine
- Patent number 11,657,040
- Issue date May 23, 2023
- Xilinx, Inc.
- Ji Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integration of a programmable device and a processing system in an...
- Patent number 11,024,583
- Issue date Jun 1, 2021
- Xilinx, Inc.
- Austin H. Lesea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Migrating virtual machines between compute systems by transmitting...
- Patent number 10,740,146
- Issue date Aug 11, 2020
- Xilinx, Inc.
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integration of a programmable device and a processing system in an...
- Patent number 10,573,598
- Issue date Feb 25, 2020
- Xilinx, Inc.
- Austin H. Lesea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Striped direct memory access circuit
- Patent number 10,474,599
- Issue date Nov 12, 2019
- Xilinx, Inc.
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Encapsulating metadata of a platform for application-specific tailo...
- Patent number 9,880,966
- Issue date Jan 30, 2018
- Xilinx, Inc.
- L. James Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compilation of system designs
- Patent number 9,805,152
- Issue date Oct 31, 2017
- Xilinx, Inc.
- Jorge E. Carrillo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic implementation of a customized system-on-chip
- Patent number 9,652,570
- Issue date May 16, 2017
- Xilinx, Inc.
- Vinod K. Kathail
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor system with performance control based on input and o...
- Patent number 9,557,795
- Issue date Jan 31, 2017
- Xilinx, Inc.
- Sabih Sabih
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for adaptively tuning an integrated circuit
- Patent number 9,444,497
- Issue date Sep 13, 2016
- Xilinx, Inc.
- Sundararajarao Mohan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compilation of HLL code with hardware accelerated functions
- Patent number 9,223,921
- Issue date Dec 29, 2015
- Xilinx, Inc.
- Jorge E. Carrillo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware and software cosynthesis performance estimation
- Patent number 9,147,024
- Issue date Sep 29, 2015
- Xilinx, Inc.
- Vinod K. Kathail
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software debugging of synthesized hardware
- Patent number 8,775,986
- Issue date Jul 8, 2014
- Xilinx, Inc.
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of a data transfer network
- Patent number 8,762,916
- Issue date Jun 24, 2014
- Xilinx, Inc.
- Vinod K. Kathail
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit providing improved feed back of a signal
- Patent number 8,327,200
- Issue date Dec 4, 2012
- Xilinx, Inc.
- Sundararajarao Mohan
Information Patent Grant
Event-driven simulation of IP using third party event-driven simula...
- Patent number 7,721,090
- Issue date May 18, 2010
- Xilinx, Inc.
- Kumar Deepak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for function acceleration using custom instructions
- Patent number 7,676,661
- Issue date Mar 9, 2010
- Xilinx, Inc.
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for designing a multiprocessor
- Patent number 7,310,594
- Issue date Dec 18, 2007
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic element with expander structures
- Patent number 7,248,073
- Issue date Jul 24, 2007
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for providing self-implementing hardware-softw...
- Patent number 7,243,330
- Issue date Jul 10, 2007
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic element with expander structures
- Patent number 7,145,360
- Issue date Dec 5, 2006
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Softpal implementation and mapping technology for FPGAs with dedica...
- Patent number 7,111,273
- Issue date Sep 19, 2006
- Xilinx, Inc.
- Satish R. Ganesan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable logic element with expander structures
- Patent number 6,847,229
- Issue date Jan 25, 2005
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable logic element with expander structures
- Patent number 6,630,841
- Issue date Oct 7, 2003
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable logic block for PLD with logic gate for combining outp...
- Patent number 6,603,332
- Issue date Aug 5, 2003
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Field programmable optical arrays
- Patent number 6,583,645
- Issue date Jun 24, 2003
- Xilinx, Inc.
- David W. Bennett
- G02 - OPTICS
Information Patent Grant
Method for implementing large multiplexers with FPGA lookup tables
- Patent number 6,505,337
- Issue date Jan 7, 2003
- Xilinx, Inc.
- Ralph D. Wittig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logic/memory circuit having a plurality of operating modes
- Patent number 6,501,296
- Issue date Dec 31, 2002
- Xilinx, Inc.
- Ralph D. Wittig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hetergeneous method for determining module placement in FPGAs
- Patent number 6,457,164
- Issue date Sep 24, 2002
- Xilinx, Inc.
- L. James Hwang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FRAMEWORK FOR SYSTEM SIMULATION USING MULTIPLE SIMULATORS
- Publication number 20230367923
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Ji Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCKCHAIN MACHINE BROADCAST PROTOCOL WITH LOSS RECOVERY
- Publication number 20230370521
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Ji YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE BLOCK PROCESSOR FOR BLOCKCHAIN MACHINE COMPUTE ACCELERATIO...
- Publication number 20230342775
- Publication date Oct 26, 2023
- Xilinx, Inc.
- Haris JAVAID
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCKCHAIN MACHINE COMPUTE ACCELERATION ENGINE WITH OUT-OF-ORDER SU...
- Publication number 20230342151
- Publication date Oct 26, 2023
- Xilinx, Inc.
- Haris JAVAID
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCKCHAIN MACHINE NETWORK ACCELERATION ENGINE
- Publication number 20220138178
- Publication date May 5, 2022
- Xilinx, Inc.
- Ji YANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCKCHAIN MACHINE COMPUTE ACCELERATION ENGINE
- Publication number 20220131704
- Publication date Apr 28, 2022
- Xilinx, Inc.
- Haris JAVAID
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATION OF A PROGRAMMABLE DEVICE AND A PROCESSING SYSTEM IN AN...
- Publication number 20200161247
- Publication date May 21, 2020
- Xilinx, Inc.
- Austin H. LESEA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATION OF A PROGRAMMABLE DEVICE AND A PROCESSING SYSTEM IN AN...
- Publication number 20190096813
- Publication date Mar 28, 2019
- Xilinx, Inc.
- Austin H. Lesea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIGRATING ACCELERATORS BETWEEN COMPUTE SYSTEMS
- Publication number 20180232254
- Publication date Aug 16, 2018
- Xilinx, Inc.
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable logic element with expander structures
- Publication number 20070035328
- Publication date Feb 15, 2007
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic element with expander structures
- Publication number 20050062498
- Publication date Mar 24, 2005
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic element with expander structures
- Publication number 20040032283
- Publication date Feb 19, 2004
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic element with expander structures
- Publication number 20020125910
- Publication date Sep 12, 2002
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic block for PLD with logic gate for combining outp...
- Publication number 20020079921
- Publication date Jun 27, 2002
- Xilinx, Inc.
- Alireza S. Kaviani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable logic element with expander structures
- Publication number 20010045844
- Publication date Nov 29, 2001
- Xilinx, Inc.
- Bernard J. New
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Logic/memory circuit having a plurality of operating modes
- Publication number 20010043082
- Publication date Nov 22, 2001
- Xilink, Inc.
- Ralph D. Wittig
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable lookup table for programmable logic devices
- Publication number 20010030555
- Publication date Oct 18, 2001
- Xilinx, Inc.
- Ralph D. Witting
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods and media for utilizing symbolic expressions in circuit mod...
- Publication number 20010001881
- Publication date May 24, 2001
- Sundararajarao Mohan
- G06 - COMPUTING CALCULATING COUNTING

Sundararajarao Mohan

Person

Patents Grantslast 30 patents

Blockchain machine compute acceleration engine with a block verify...

Blockchain machine network acceleration engine

Integration of a programmable device and a processing system in an...

Migrating virtual machines between compute systems by transmitting...

Integration of a programmable device and a processing system in an...

Striped direct memory access circuit

Encapsulating metadata of a platform for application-specific tailo...

Compilation of system designs

Automatic implementation of a customized system-on-chip

Multiprocessor system with performance control based on input and o...

Method and apparatus for adaptively tuning an integrated circuit

Compilation of HLL code with hardware accelerated functions

Hardware and software cosynthesis performance estimation

Software debugging of synthesized hardware

Automatic generation of a data transfer network

Integrated circuit providing improved feed back of a signal

Event-driven simulation of IP using third party event-driven simula...

Method and system for function acceleration using custom instructions

Method and system for designing a multiprocessor

Configurable logic element with expander structures

Method and apparatus for providing self-implementing hardware-softw...

Configurable logic element with expander structures

Softpal implementation and mapping technology for FPGAs with dedica...

Configurable logic element with expander structures

Configurable logic element with expander structures

Configurable logic block for PLD with logic gate for combining outp...

Field programmable optical arrays

Method for implementing large multiplexers with FPGA lookup tables

Logic/memory circuit having a plurality of operating modes

Hetergeneous method for determining module placement in FPGAs

Patents Applicationslast 30 patents

FRAMEWORK FOR SYSTEM SIMULATION USING MULTIPLE SIMULATORS

BLOCKCHAIN MACHINE BROADCAST PROTOCOL WITH LOSS RECOVERY

ADAPTIVE BLOCK PROCESSOR FOR BLOCKCHAIN MACHINE COMPUTE ACCELERATIO...

BLOCKCHAIN MACHINE COMPUTE ACCELERATION ENGINE WITH OUT-OF-ORDER SU...

BLOCKCHAIN MACHINE NETWORK ACCELERATION ENGINE

BLOCKCHAIN MACHINE COMPUTE ACCELERATION ENGINE

INTEGRATION OF A PROGRAMMABLE DEVICE AND A PROCESSING SYSTEM IN AN...

INTEGRATION OF A PROGRAMMABLE DEVICE AND A PROCESSING SYSTEM IN AN...

MIGRATING ACCELERATORS BETWEEN COMPUTE SYSTEMS

Configurable logic element with expander structures

Configurable logic element with expander structures

Configurable logic element with expander structures

Configurable logic element with expander structures

Configurable logic block for PLD with logic gate for combining outp...

Configurable logic element with expander structures

Logic/memory circuit having a plurality of operating modes

Configurable lookup table for programmable logic devices

Methods and media for utilizing symbolic expressions in circuit mod...