Sungryul Kim

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transistor noise tolerant, non-volatile (NV) resistance element-bas...
- Patent number 10,803,942
- Issue date Oct 13, 2020
- QUALCOMM Technologies, Inc.
- Seong-Ook Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic memory protection
- Patent number 10,740,017
- Issue date Aug 11, 2020
- QUALCOMM Incorporated
- Chando Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) de...
- Patent number 10,636,962
- Issue date Apr 28, 2020
- QUALCOMM Incorporated
- Chando Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Magneto-resistive random access memory (MRAM) employing an integrat...
- Patent number 10,460,780
- Issue date Oct 29, 2019
- QUALCOMM Incorporated
- Sungryul Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-speed, low power spin-orbit torque (SOT) assisted spin-transfe...
- Patent number 10,381,060
- Issue date Aug 13, 2019
- QUALCOMM Incorporated
- Jimmy Jianan Kan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV)...
- Patent number 10,319,425
- Issue date Jun 11, 2019
- QUALCOMM Technologies Incorporated
- Seong-Ook Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
One-time programming (OTP) magneto-resistive random access memory (...
- Patent number 10,311,930
- Issue date Jun 4, 2019
- QUALCOMM Incorporated
- Sungryul Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Offset-canceling (OC) write operation sensing circuits for sensing...
- Patent number 10,290,340
- Issue date May 14, 2019
- Qualcomm Technologies, Incorporated
- Seong-Ook Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction and decoding
- Patent number 10,263,645
- Issue date Apr 16, 2019
- QUALCOMM Incorporated
- Seong-Ook Jung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic memory protection
- Patent number 10,249,814
- Issue date Apr 2, 2019
- QUALCOMM Incorporated
- Chando Park
- G01 - MEASURING TESTING
Information Patent Grant
Sensing voltage based on a supply voltage applied to magneto-resist...
- Patent number 10,224,087
- Issue date Mar 5, 2019
- Qualcomm Technologies, Incorporated
- Seong-Ook Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Data bit inversion tracking in cache memory to reduce data bits wri...
- Patent number 10,115,444
- Issue date Oct 30, 2018
- QUALCOMM Incorporated
- Hyunsuk Shin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error correction and decoding
- Patent number 9,800,271
- Issue date Oct 24, 2017
- QUALCOMM Incorporated
- Seong-Ook Jung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-step programming of heat-sensitive non-volatile memory (NVM)...
- Patent number 9,753,874
- Issue date Sep 5, 2017
- QUALCOMM Incorporated
- Adam Edward Newham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MRAM word line power control scheme
- Patent number 9,672,885
- Issue date Jun 6, 2017
- QUALCOMM Incorporated
- Sungryul Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Shared built-in self-analysis of memory systems employing a memory...
- Patent number 9,653,183
- Issue date May 16, 2017
- QUALCOMM Incorporated
- Hyunsuk Shin
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage self-boosting circuit for generating a boosted voltage for...
- Patent number 9,633,706
- Issue date Apr 25, 2017
- QUALCOMM Incorporated
- Sungryul Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Performing memory data scrubbing operations in processor-based memo...
- Patent number 9,612,908
- Issue date Apr 4, 2017
- QUALCOMM Incorporated
- Taehyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write driver circuits for resistive random access memory (RAM) arrays
- Patent number 9,583,171
- Issue date Feb 28, 2017
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjusting resistive memory write driver strength based on a mimic r...
- Patent number 9,583,170
- Issue date Feb 28, 2017
- QUALCOMM Incorporated
- Taehyun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Real time correction of bit failure in resistive memory
- Patent number 9,552,244
- Issue date Jan 24, 2017
- QUALCOMM Incorporated
- Taehyun Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for reducing memory failures
- Patent number 9,495,261
- Issue date Nov 15, 2016
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Adjusting resistive memory write driver strength based on write err...
- Patent number 9,455,014
- Issue date Sep 27, 2016
- QUALCOMM Incorporated
- Kangho Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method to trim reference levels in a resistive memory
- Patent number 9,455,013
- Issue date Sep 27, 2016
- QUALCOMM Incorporated
- Taehyun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable read delay system
- Patent number 9,431,129
- Issue date Aug 30, 2016
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM initialization devices and methods
- Patent number 9,401,226
- Issue date Jul 26, 2016
- QUALCOMM Incorporated
- Hyunsuk Shin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for generating a reference for use with a magn...
- Patent number 9,336,847
- Issue date May 10, 2016
- QUALCOMM Incorporated
- Sungryul Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Read operation of MRAM using a dummy word line
- Patent number 9,275,714
- Issue date Mar 1, 2016
- QUALCOMM Incorporated
- Taehyun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit recovery system
- Patent number 9,262,263
- Issue date Feb 16, 2016
- QUALCOMM Incorporated
- Taehyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to trim reference levels in a resistive memory
- Patent number 9,251,881
- Issue date Feb 2, 2016
- QUALCOMM Incorporated
- Taehyun Kim
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SPIN-ORBIT TORQUE (SOT) MAGNETIC TUNNEL JUNCTION (MTJ) (SOT-MTJ) DE...
- Publication number 20200066968
- Publication date Feb 27, 2020
- QUALCOMM Incorporated
- Chando Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC MEMORY PROTECTION
- Publication number 20190332306
- Publication date Oct 31, 2019
- QUALCOMM Incorporated
- Chando PARK
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Application
MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) EMPLOYING AN INTEGRAT...
- Publication number 20190304527
- Publication date Oct 3, 2019
- QUALCOMM Incorporated
- Sungryul Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH SPEED, LOW POWER SPIN-ORBIT TORQUE (SOT) ASSISTED SPIN-TRANSFE...
- Publication number 20180061467
- Publication date Mar 1, 2018
- QUALCOMM Incorporated
- Jimmy Jianan KAN
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR CORRECTION AND DECODING
- Publication number 20180019767
- Publication date Jan 18, 2018
- QUALCOMM Incorporated
- Seong-Ook JUNG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CORRECTION AND DECODING
- Publication number 20170077963
- Publication date Mar 16, 2017
- QUALCOMM Incorporated
- Seong-Ook JUNG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER GATING DEVICES AND METHODS
- Publication number 20170070225
- Publication date Mar 9, 2017
- QUALCOMM Incorporated
- Jung Pill KIM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON WRITE ERR...
- Publication number 20160276009
- Publication date Sep 22, 2016
- QUALCOMM Incorporated
- Kangho Lee
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE DRIVER CIRCUITS FOR RESISTIVE RANDOM ACCESS MEMORY (RAM) ARRAYS
- Publication number 20160267959
- Publication date Sep 15, 2016
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Application
PERFORMING MEMORY DATA SCRUBBING OPERATIONS IN PROCESSOR-BASED MEMO...
- Publication number 20160246679
- Publication date Aug 25, 2016
- QUALCOMM Incorporated
- Taehyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-STEP PROGRAMMING OF HEAT-SENSITIVE NON-VOLATILE MEMORY (NVM)...
- Publication number 20160246608
- Publication date Aug 25, 2016
- QUALCOMM Incorporated
- Adam Edward Newham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON A MIMIC R...
- Publication number 20160240237
- Publication date Aug 18, 2016
- QUALCOMM Incorporated
- Taehyun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY
- Publication number 20160125926
- Publication date May 5, 2016
- QUALCOMM Incorporated
- Taehyun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
VARIABLE READ DELAY SYSTEM
- Publication number 20150318057
- Publication date Nov 5, 2015
- QUALCOMM Incorporated
- Jung Pill KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY
- Publication number 20150310904
- Publication date Oct 29, 2015
- QUALCOMM Incorporated
- Taehyun KIM
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR GENERATING A REFERENCE FOR USE WITH A MAG...
- Publication number 20150302912
- Publication date Oct 22, 2015
- QUALCOMM Incorporated
- Sungryul Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR REDUCING MEMORY FAILURES
- Publication number 20150261632
- Publication date Sep 17, 2015
- QUALCOMM Incorporated
- Jung Pill KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REAL TIME CORRECTION OF BIT FAILURE IN RESISTIVE MEMORY
- Publication number 20150194201
- Publication date Jul 9, 2015
- QUALCOMM Incorporated
- Taehyun KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT RECOVERY SYSTEM
- Publication number 20150149864
- Publication date May 28, 2015
- QUALCOMM Incorporated
- Taehyun Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE PULSE WIDTH SCHEME IN A RESISTIVE MEMORY
- Publication number 20150117086
- Publication date Apr 30, 2015
- QUALCOMM Incorporated
- Taehyun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE DRIVER AND PROGRAM DRIVER FOR OTP (ONE-TIME PROGRAMMABLE) MEM...
- Publication number 20150103586
- Publication date Apr 16, 2015
- QUALCOMM Incorporated
- Sungryul Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY
- Publication number 20150092469
- Publication date Apr 2, 2015
- QUALCOMM Incorporated
- Taehyun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL
- Publication number 20150070978
- Publication date Mar 12, 2015
- QUALCOMM Incorporated
- Taehyun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION
- Publication number 20150022264
- Publication date Jan 22, 2015
- QUALCOMM Incorporated
- Jung Pill Kim
- G01 - MEASURING TESTING
Information Patent Application
ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS
- Publication number 20140215294
- Publication date Jul 31, 2014
- QUALCOMM Incorporated
- Jung Pill Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL ARRAY WITH RESERVED SECTOR FOR STORING CONFIGURATION IN...
- Publication number 20140140162
- Publication date May 22, 2014
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Application
OTP SCHEME WITH MULTIPLE MAGNETIC TUNNEL JUNCTION DEVICES IN A CELL
- Publication number 20140071740
- Publication date Mar 13, 2014
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Application
REFERENCE CELL REPAIR SCHEME
- Publication number 20140071738
- Publication date Mar 13, 2014
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Application
REFERENCE LEVEL ADJUSTMENT SCHEME
- Publication number 20140071739
- Publication date Mar 13, 2014
- QUALCOMM Incorporated
- Jung Pill Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM WORD LINE POWER CONTROL SCHEME
- Publication number 20140063922
- Publication date Mar 6, 2014
- QUALCOMM Incorporated
- Sungryul Kim
- G11 - INFORMATION STORAGE

Sungryul Kim

Person

Patents Grantslast 30 patents

Transistor noise tolerant, non-volatile (NV) resistance element-bas...

Dynamic memory protection

Spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) de...

Magneto-resistive random access memory (MRAM) employing an integrat...

High-speed, low power spin-orbit torque (SOT) assisted spin-transfe...

Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV)...

One-time programming (OTP) magneto-resistive random access memory (...

Offset-canceling (OC) write operation sensing circuits for sensing...

Error correction and decoding

Dynamic memory protection

Sensing voltage based on a supply voltage applied to magneto-resist...

Data bit inversion tracking in cache memory to reduce data bits wri...

Error correction and decoding

Multi-step programming of heat-sensitive non-volatile memory (NVM)...

MRAM word line power control scheme

Shared built-in self-analysis of memory systems employing a memory...

Voltage self-boosting circuit for generating a boosted voltage for...

Performing memory data scrubbing operations in processor-based memo...

Write driver circuits for resistive random access memory (RAM) arrays

Adjusting resistive memory write driver strength based on a mimic r...

Real time correction of bit failure in resistive memory

Systems and methods for reducing memory failures

Adjusting resistive memory write driver strength based on write err...

System and method to trim reference levels in a resistive memory

Variable read delay system

MRAM initialization devices and methods

Method and apparatus for generating a reference for use with a magn...

Read operation of MRAM using a dummy word line

Bit recovery system

System and method to trim reference levels in a resistive memory

Patents Applicationslast 30 patents

SPIN-ORBIT TORQUE (SOT) MAGNETIC TUNNEL JUNCTION (MTJ) (SOT-MTJ) DE...

DYNAMIC MEMORY PROTECTION

MAGNETO-RESISTIVE RANDOM ACCESS MEMORY (MRAM) EMPLOYING AN INTEGRAT...

HIGH SPEED, LOW POWER SPIN-ORBIT TORQUE (SOT) ASSISTED SPIN-TRANSFE...

ERROR CORRECTION AND DECODING

ERROR CORRECTION AND DECODING

POWER GATING DEVICES AND METHODS

ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON WRITE ERR...

WRITE DRIVER CIRCUITS FOR RESISTIVE RANDOM ACCESS MEMORY (RAM) ARRAYS

PERFORMING MEMORY DATA SCRUBBING OPERATIONS IN PROCESSOR-BASED MEMO...

MULTI-STEP PROGRAMMING OF HEAT-SENSITIVE NON-VOLATILE MEMORY (NVM)...

ADJUSTING RESISTIVE MEMORY WRITE DRIVER STRENGTH BASED ON A MIMIC R...

SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY

VARIABLE READ DELAY SYSTEM

SYSTEM AND METHOD OF CONCURRENT READ/WRITE MAGNETO-RESISTIVE MEMORY

METHOD AND APPARATUS FOR GENERATING A REFERENCE FOR USE WITH A MAG...

SYSTEMS AND METHODS FOR REDUCING MEMORY FAILURES

REAL TIME CORRECTION OF BIT FAILURE IN RESISTIVE MEMORY

BIT RECOVERY SYSTEM

WRITE PULSE WIDTH SCHEME IN A RESISTIVE MEMORY

WRITE DRIVER AND PROGRAM DRIVER FOR OTP (ONE-TIME PROGRAMMABLE) MEM...

SYSTEM AND METHOD TO TRIM REFERENCE LEVELS IN A RESISTIVE MEMORY

SYSTEM AND METHOD TO PROVIDE A REFERENCE CELL

SENSE AMPLIFIER OFFSET VOLTAGE REDUCTION

ERROR DETECTION AND CORRECTION OF ONE-TIME PROGRAMMABLE ELEMENTS

MEMORY CELL ARRAY WITH RESERVED SECTOR FOR STORING CONFIGURATION IN...

OTP SCHEME WITH MULTIPLE MAGNETIC TUNNEL JUNCTION DEVICES IN A CELL

REFERENCE CELL REPAIR SCHEME

REFERENCE LEVEL ADJUSTMENT SCHEME

MRAM WORD LINE POWER CONTROL SCHEME